Clock generating circuit

• US 6,781,431 B2
• Filed: 01/23/2003
• Issued: 08/24/2004
• Est. Priority Date: 09/19/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubshi Electric Engineering Company Limited (Mitsubishi Electric Corporation), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Morishita, Fukashi, Fujii, Nobuyuki, Yamazaki, Akira, Akiyama, Mihoko, Taito, Yasuhiko, Okamoto, Mako
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/349,033
• Publication Number:
  US 20030117204A1
• Time in Patent Office: 579 Days
• Field of Search: 327/291, 327/101, 327/105, 327/113, 327/114, 327/164-166, 327/256-258, 327/293-295, 326/93-95, 331/57
• US Class Current: 327/291
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/70 time intervals between all adjacent pulses of one train being equal

Abstract

The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

Claims

1. A clock generating circuit generating a clock signal comprising:

a ring oscillator including an odd number of first inverters connected in a ring configuration, being activated to generate a clock signal when an activating signal is at a first level, while being deactivated to cease generation of said clock signal when said activating signal is at a second level; and

a latch circuit, connected to an output node of said ring oscillator, and holding a level of the output node of said ring oscillator in response to transition of said activating signal from said first level to said second level,

wherein the output node of said ring oscillator is an internal node in the ring configuration and the level of the output node of the ring oscillator is driven to one of a high level and a low level in accordance with the timing of the activating signal driven to the second level from the first level.

2. The clock generating circuit according to claim 1, wherein one first inverter of said odd number of first inverters is a clocked inverter that is activated when said activating signal is at said first level, while being deactivated when said activating signal is at said second level, and whose output node serves as the output node of said ring oscillator.

3. The clock generating circuit according to claim 1, wherein said ring oscillator further includes:

a transfer gate inserted between an output node of one first inverter of said odd number of first inverters and an input node of the subsequent first inverter thereof, and being conductive when said activating signal is at said first level, while being nonconductive when said activating signal is at said second level, wherein said input node of said subsequent inverter serves as the output node of said ring oscillator.

4. The clock generating circuit according to claim 1, wherein a first inverter includes:

first and second transistors of respective different conductivity types connected in series between first and second power source potential lines; and

at least one constant current source connected in series to said first and second transistors between said first and second power source potential lines.

5. The clock generating circuit according to claim 1, wherein said clock signal is used as a driving clock signal for a charge pump circuit.

6. The clock generating circuit according to claim 1, wherein said latch circuit further comprising:

a second inverter connected between the output node of said ring oscillator and an output node of said clock generating circuit; and

a clocked inverter, in inverse parallel connection to said second inverter, being deactivated when said activating signal is at said first level, while being activated when said activating signal is at said second level.

7. The clock generating circuit according to claim 6, further comprising:

at least three of said second inverter, which are connected in series between the output node of said ring oscillator and an output node of said clock generating circuit.

8. The clock generating circuit according to claim 6, further comprising:

a noise filter inserted between an output node of said second inverter and an output node of said clock generating circuit, and for eliminating noise from an output signal of said second inverter.