Failsafe differential amplifier circuit

• US 6,781,456 B2
• Filed: 11/12/2002
• Issued: 08/24/2004
• Est. Priority Date: 11/12/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pradhan, Pravas
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US10/292,119
• Publication Number:
  US 20040090265A1
• Time in Patent Office: 651 Days
• Field of Search: 330/69, 326/14, 327/64, 327/205
• US Class Current: 330/69
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is detected and signaled. The output signal form the fail safe circuitry is held in a given state that is an invalid representation of the differential input signal. A frequency detector, complementary offsetting auxiliary amplifiers with limit frequency roll offs are used to detect the fail safe condition. In addition a delay circuit is used that requires the fail safe condition to exist for some time before the fail safe circuit is active. Initialization circuitry ensures a proper power up conditions where the circuitry is enabled to detect the fail safe conditions and guarantees a reliable fail safe irrespective of the previous state of the signal.

Claims

1. A fail safe differential receiver circuit wherein a fail safe condition includes loss in amplitude of the input differential signal and wherein signal frequency is lower than a defined limit, the circuit comprising:

a differential amplifier,

two complementary auxiliary differential amplifiers, each auxiliary amplifier incorporating complementary offset voltages set to a value,

wherein the input differential signal is connected to the differential inputs of the differential amplifier and of the two auxiliary amplifiers,

a frequency detector that detects when the input differential signal is less than a frequency limit,

a logic circuit that receives inputs from the frequency detector and the two auxiliary amplifiers, wherein the logic circuit determines that, when the differential signal amplitude is less than the value and the frequency is less than the frequency limit, the logic circuit fail safe condition is activated.

2. The fail safe circuit of claim 1 further comprising:

a time delay arranged for delaying the fail safe condition signal.

3. The fail safe circuit of claim 1 further comprising an initialization circuit that enables the fail safe circuit to operate.

4. The fail safe circuit of claim 1 wherein the auxiliary amplifiers have a frequency roll off at the signal frequency limit.

5. A computing system selected from the group consisting of computer communications systems, displays, computerized instruments, data gathering and distributed systems, the computing system comprising at least one fail safe differential receiver circuit as defined in claim 1.

6. A method for determining a fail safe condition in a differential receiver circuit wherein fail safe is defined as a loss in amplitude and frequency of the input differential signal with respect to defined thresholds, the method comprising the steps of:

comparing the amplitude of the input differential signal to a defined amplitude threshold,

comparing the frequency of the input differential signal to a defined frequency threshold,

logically determining that if the differential signal amplitude is less than the amplitude threshold, and if the frequency is less than the frequency threshold, then

asserting a fail safe condition.