Method and apparatus for differential signal detection

• US 6,781,465 B1
• Filed: 12/13/2002
• Issued: 08/24/2004
• Est. Priority Date: 12/13/2002
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Berzins, Matthew S., Cornell, Charles A., Prather, Stephen M.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/318,543
• Time in Patent Office: 620 Days
• Field of Search: 330/258, 330/69
• US Class Current: 330/258
• CPC Class Codes: H03F 3/4508 using bipolar transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.

Claims

1. A differential signal detection device comprising:

a first differential amplifier coupled to a first differential input and a second differential input, the first differential amplifier including a first leg having a first set of components and a second leg having a second set of components, the first set of components not matching the second set of components;

a second differential amplifier coupled to the first differential input and the second differential input, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third set of components not matching the fourth set of components; and

an indication circuit coupled to the first differential amplifier and the second differential amplifier, the indication circuit structured to generate a signal based on output signals from the first and second differential amplifiers.

2. The device of claim 1,

wherein the first leg and second leg are coupled in parallel between a supply voltage and a first current source, the first current source being connected to a reference voltage;

wherein the first and second sets of components each include a respective load element coupled to a respective transistor;

wherein the first differential input is coupled to a gate of the respective transistor in the first leg and the second differential input is coupled to a gate of the respective transistor in the second leg; and

wherein an additional component is coupled to a drain of the respective transistor in one of the first or second legs.

3. The device of claim 2,

wherein the third leg and the fourth leg are connected in parallel between the supply voltage and a second current source, the second current source being connected to the reference voltage;

wherein the third and fourth sets of components each include a respective load element coupled to a respective transistor;

wherein the first differential input is coupled to a gate of the respective transistor in the third leg and the second differential input is coupled to a gate of the respective transistor in the fourth leg, and

wherein an additional component is coupled to a drain of the respective transistor in one of the third or fourth legs.

4. The device of claim 3, wherein at least one of the load elements is an active load.

5. The device of claim 1,

wherein one of the legs in the first differential amplifier includes a first resistance not present in the other leg of the first differential amplifier;

wherein one of the legs in the second differential amplifier includes a second resistance not present in the other leg of the second differential amplifier,

wherein the first and second resistances are substantially equal to one another; and

wherein the first and second differential amplifiers have a gain equal to one.

6. The device of claim 1, wherein the indication circuit comprises:

an OR gate having inputs coupled to the first, second, third, and fourth legs; and

a buffer, having an input coupled to an output of the OR gate.

7. The device of claim 1,

wherein the first and the second differential inputs are respectively coupled to a first and second signal line of a universal serial bus.

8. A data bus signal detection system comprising:

a first input terminal structured to be coupled to a first signal line of a data bus;

a second input terminal structured to be coupled to a second signal line of the data bus;

a first differential amplifier coupled to the first input terminal and the second input terminal, the f differential amplifier including a first leg having a first set of components and a second leg having a second set of components, the first set of components not matching the second set of components;

a second differential amplifier coupled to the first input terminal and the second input terminal, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third set of components not matching the fourth set of components; and

an indication circuit structured to produce a signal based on output signals from the first and second differential amplifiers.

9. The system of claim 8,

wherein the first leg and second leg are coupled in parallel between a supply voltage and a first current source, the first current source being coupled to a reference voltage;

wherein the first and second sets of components each include a respective load element coupled to a respective transistor;

wherein the first input terminal is coupled to a gate of the transistor in the first leg and the second input terminal is coupled to a gate of the transistor in the second leg; and

wherein an additional component is coupled to a drain of the transistor in one of the first or second legs.

10. The system of claim 9,

wherein the third leg and the fourth leg are coupled in parallel between the supply voltage and a second current source, the second current source being coupled to the reference voltage;

wherein the third and fourth sets of components each include a respective load element coupled to a respective transistor;

wherein the first input terminal is coupled to a gate of the transistor in the third leg and the second input terminals coupled to a gate of the transistor in the fourth leg, and

wherein an additional component is coupled to a drain of the transistor in one of the third or fourth legs.

11. The system of claim 10, wherein at least one of the load elements is an active load.

12. The system of claim 8,

wherein one of the legs in the first differential amplifier further comprises a first resistance not present in the other leg of the first differential amplifier;

wherein one of the legs in the second differential amplifier further comprises a second resistance not present in the other leg of the second differential amplifier;

wherein the first and second resistances are substantially equal to one another; and

wherein the first and second differential amplifiers have a gain equal to one.

13. The system of claim 8, wherein the indication circuit comprises:

an OR gate having inputs coupled to the first, second, third, and fourth legs; and

a buffer having an input coupled to an output of the OR gate.

14. The system of claim 8,

wherein the first and the second input terminals are respectively coupled to a first and second signal line of a universal serial bus.

15. A method for detecting differential signals comprising:

applying a first differential signal to a first leg of a first differential amplifier and a second differential signal to a second leg of the first differential amplifier, wherein the first and second legs of the first differential amplifier are dissimilar from one another;

applying the first differential signal to a first leg of a second differential amplifier and the second differential signal to a second leg of the second differential amplifier, wherein the first and second legs of the second differential amplifier are dissimilar from one another;

comparing signals from the legs in the first and second differential amplifiers in a logic circuit; and

generating an output from the logic circuit based on the comparison.

16. The method of claim 15, wherein applying a first differential signal to a first leg of a first differential amplifier and a second differential signal to a second leg of the first differential amplifier comprises coupling the first differential signal to a first data signal of a universal serial bus, and coupling the second differential signal to a second data signal of the universal serial bus.

17. The method of claim 16, wherein applying the first differential signal to a first leg of a second differential amplifier and the second differential signal to a second leg of the second differential amplifier comprises coupling the first differential signal to a first data signal of a universal serial bus, and coupling the second differential signal to a second data signal of the universal serial bus.

18. The method of claim 17, wherein comparing signals from the legs in the first and second differential amplifiers comprises:

accepting signals from the first and second legs of the first differential amplifier, and from the first and second legs of the second differential amplifier, the first and second differential amplifiers having a gain equal to one; and

performing a logic operation on the accepted signals.

19. The method of claim 18, wherein performing a logic operation comprises performing an OR function.

20. The method of claim 19, wherein generating an output from the logic circuit comprises buffering a signal produced as a result of performing the OR function.

21. A differential signal detection device comprising:

a first differential amplifier with a gain substantially equal to one coupled to a first differential input and a second differential input, the first differential amplifier including a first leg having a first set of components and a second leg having a second set of components, the first set of components not matching the second set of components, the first leg including a fist resistance not present in the second leg;

a second differential amplifier with a gain substantially equal to one coupled to the first differential input and the second differential input, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third leg including a second resistance not present in the fourth leg, the first and second resistances substantially equal to each other; and

an indication circuit coupled to the first differential amplifier and the second differential amplifier, the indication circuit structured to generate a signal based on output signals from the first and second differential amplifiers.

22. A differential signal detection device comprising:

a first differential amplifier coupled to a first differential input and a second differential input, the first differential amplifier including a first leg having a first set of components and a second leg having a second set of components, the first set of components not matching the second set of components;

a second differential amplifier coupled to the first differential input and the second differential input, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third set of components not matching the fourth set of components; and

an indication circuit coupled to the first differential amplifier and the second differential amplifier, the indication circuit structured to generate a signal based on output signals from the first and second differential amplifiers, the indication circuit including an OR gate having inputs coupled to the first, second, third and fourth legs and a buffer having an input coupled to an output of the OR gate.

23. A data bus signal detection system comprising:

a first input terminal;

a second input terminal;

a first differential amplifier with a gain substantially equal to one coupled to the first input terminal and the second input terminal, the first differential amplifier including a first leg having a first set of components and a second leg having a second set of components, the first leg having a first resistance not present in the second leg;

a second differential amplifier with a gain substantially equal to one coupled to the first input terminal and the second input terminal, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third leg having a second resistance not present in the fourth leg, the first and second resistances substantially equal to each other; and

an indication circuit structured to produce a signal based on output signals from the first and second differential amplifiers.

24. A data bus signal detection system comprising:

a first input terminal;

a second input terminal;

a first differential amplifier coupled to the first input terminal and the second input terminal, the first differential amplifier including a first leg having a first set of components and a second leg having a second sot of components, the first set of components not matching the second set of components;

a second differential amplifier coupled to the first input terminal and the second input terminal, the second differential amplifier including a third leg having a third set of components and a fourth leg having a fourth set of components, the third set of components not matching the fourth set of components; and

an indication circuit structured to produce a signal based on output signals from the first and second differential amplifiers, the indication circuit including an OR gate coupled to the first, second, third, and fourth legs and a buffer having an input coupled to an output of the OR gate.