Broadband chip antenna

• US 6,781,545 B2
• Filed: 08/30/2002
• Issued: 08/24/2004
• Est. Priority Date: 05/31/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Sung, Jae Suk
• Primary Examiner(s): Ho, Tan
• Application Number:
  US10/230,981
• Publication Number:
  US 20030222827A1
• Time in Patent Office: 725 Days
• Field of Search: 343/700.MS, 343/702, 343/846, 343/848, 343/767, 343/770
• US Class Current: 343/700.0MS
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 13/10 Resonant slot antennas

Abstract

Disclosed is a chip antenna including first and second electrode patterns serving as radiation elements as well as a power-feeding element and a ground element, respectively. The first and second electrode patterns are separated from each other by first and second slits. The dimension of the electrode patterns is increased by extending the width of the first electrode pattern to correspond to the length of the first slit, and the first and second electrode patterns form the successive resonant length via the second slit. The chip antenna of the present invention has a broad usable frequency band. This broadband chip antenna of the present invention may be achieved as a super broadband chip antenna with multi-band characteristics. The frequency characteristics of the chip antenna may be easily adjusted by varying the width of the slit and the length of the electrode pattern or by forming a supplementary slit or an open area.

Claims

1. A chip antenna comprising:

a dielectric block including a first surface, a second surface being opposite to the first surface, and side surfaces being disposed between the first and second surfaces;

a first electrode pattern extending from a feeding port area formed on the first surface to the second surface via one side surface adjacent to the feeding port area; and

a second electrode pattern extending from a ground port area formed on the first surface to the second surface via the other side surface adjacent to the ground port area,

wherein a first slit is formed as an open area for connecting two opposite sides of the first surface so as to electrically separate the feeding port area of the first electrode pattern from the ground port area of the second electrode pattern, and a second slit is formed in the same direction as the first slit as another open area for connecting two opposite sides of the second surface so as to form an electromagnetic coupling between the first and second electrode patterns.

2. The chip antenna as set forth in claim 1, wherein the first electrode pattern extends so that a length of one side adjacent to the first slit is substantially the same as a length of the other side adjacent to the second slit.

3. The chip antenna as set forth in claim 1, wherein the second electrode pattern extends so that a length of one side adjacent to the first slit is substantially the same as a length of the other side adjacent to the second slit.

4. The chip antenna as set forth in claim 1, wherein an extending length L1 of the first electrode pattern differs from an extending length L2 of the second electrode pattern.

5. The chip antenna as set forth in claim 1, wherein resonant frequency characteristics of the chip antenna are adjusted by varying a width of the second slit.

6. The chip antenna as set forth in claim 1, wherein resonant frequency characteristics of the chip antenna are adjusted by varying an extending length L1 of the first electrode pattern and/or an extending length L2 of the second electrode pattern.

7. The chip antenna as set forth in claim 1, further comprising at least one supplementary slit formed on the first or second electrode pattern in order to separate the first or second electrode pattern into two electrode pattern areas.

8. The chip antenna as set forth in claim 7, wherein one end of the supplementary slit is connected to the first slit and the other end of the supplementary slit is opened along the side surface on which the first or second electrode pattern is formed.

9. The chip antenna as set forth in claim 7, wherein one end of the supplementary slit is connected to the second slit and the other end of the supplementary slit is opened along the side surface on which the first or second electrode pattern is formed.

10. The chip antenna as set forth in claim 7, wherein the supplementary slit is connected to two opposite sides in the same direction of the first slit on the first or second electrode pattern, and the first or second electrode pattern is divided to an electrode pattern area including the feeding port area or the ground port area and another electrode pattern area connected to the second slit by the supplementary slit.

11. The chip antenna as set forth in claim 10, wherein the supplementary slit is formed on the side surface provided with the first or second electrode pattern.

12. The chip antenna as set forth in claim 1, wherein the first or second electrode pattern includes at least one open area on which an electrode is not formed.

13. The chip antenna as set forth in claim 12, wherein at least one of the open areas has its one end disposed within the first or second electrode pattern and its the other end opened to other side surface adjacent to the first or second electrode pattern.

14. The chip antenna as set forth in claim 12, wherein the open area is formed on the first or second surface.

15. The chip antenna as set forth in claim 14, wherein the open area is extended to the side surface adjacent to the first or second surface.

16. The chip antenna as set forth in claim 12, wherein at least one of the open areas is disposed within the first or second electrode pattern.

17. A chip antenna comprising:

a dielectric block including a upper surface, a lower surface, and side surfaces being disposed between the upper and lower surfaces;

an electrode formed on the entire surfaces of the upper and lower surface, and two opposite side surfaces; and

slits for connecting opposite sides of two side surfaces without the electrode and dividing the electrode to a first electrode pattern and a second electrode pattern, each of the slits being formed on the upper and lower surfaces of the dielectric block,

wherein the slit formed on the lower surface of the dielectric block at least separates a feeding port area from a ground port area, and the other slit formed on the upper surface of the dielectric block connects the first electrode pattern to the second electrode patterns by an EM(Electro-Magnetic) coupling.