Graphic processing system having bus connection control functions

• US 6,781,590 B2
• Filed: 11/19/2001
• Issued: 08/24/2004
• Est. Priority Date: 10/06/1986
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Kikuchi, Masahiko, Sato, Jun, Matsuo, Shigeru, Yokota, Yoshikazu, Sone, Takashi, Katsura, Koyo
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/988,157
• Publication Number:
  US 20030001850A1
• Time in Patent Office: 1,009 Days
• Field of Search: 345/501-503, 345/530, 345/545, 345/549, 345/559, 345/589, 345/596, 345/597-599
• US Class Current: 345/538
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 11/203 Drawing of straight lines or curves
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A graphic processing system having a main memory for storing a program and information corresponding to pixels, a main processor for executing a program transferred from the main memory or from external to control the system, display/output devices for outputting graphic information attained by a control of pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels output to the display/output devices, and a graphic processor for receiving a command and parameter information from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure, and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or frame buffer.

Claims

1. A graphic processing system comprising:

a main memory;

a graphic memory holding graphic data;

a graphic processor which is connected to said graphic memory and generates graphic data to be written into said graphic memory;

a first signal line connected to said main memory to transfer data between said main memory and said graphic processor;

a second signal line connected to said graphic processor; and

a switch provided between said first signal line and said second signal line,

wherein said graphic processor comprises;

at least a control unit which generates a control signal for controlling said switch thereby causing said switch to select one of said first signal line and said second signal line, and

a color register holding color data,

wherein the control signal generated by said control unit is provided to said switch to read out data stored in said main memory and designate one among the color data held in said color register in accordance with the contents of the read-out data, and write the designated color data into said graphic memory.

2. A graphic processing system according to claim 1, wherein said graphic memory is connected to said second signal line.

3. A graphic processing system according to claim 1, wherein data read out from said main memory is at least one-bit data, and said color data is designated based on a value of the one-bit data.

4. A graphic processing system according to claim 1, wherein said color data is a gradation data representing a gradation.

5. A graphic processing system comprising:

a first memory storing instructions and data;

a second memory holding graphic data;

a graphic processor which is connected to said second memory and generates a graphic data to be written into said second memory;

a first signal line connected to said first memory to transfer data between said first memory and said graphic processor;

a second signal line connected to said graphic processor; and

a switch provided between said first signal line and said second signal line,

wherein said graphic processor comprises;

at least a control unit which generates a control signal for controlling said switch thereby causing said switch to select one of said first signal line and said second signal line, and

a color register holding color data,

wherein the control signal generated by said control unit is provided to said switch to read out data stored in said first memory and designate one among the color data held in said color register in accordance with the contents of the read-out data, and write the designated color data into said second memory.

6. A graphic processing system according to claim 5, wherein said second memory is connected to said second signal line.

7. A graphic processing system according to claim 5, wherein data read out from said first memory is at least one-bit data, and said color data is designated based on a value of the one-bit data.

8. A graphic processing system according to claim 5, wherein said color data is gradation data representing a gradation.