Cubic memory array

• US 6,781,858 B2
• Filed: 08/29/2003
• Issued: 08/24/2004
• Est. Priority Date: 04/02/2002
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter, Anderson, Daryl
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): HUR, JUNG H
• Application Number:
  US10/650,895
• Publication Number:
  US 20040042313A1
• Time in Patent Office: 361 Days
• Field of Search: 365/51, 365/63, 365/105, 365/96
• US Class Current: 365/51
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

Claims

1. A cubic memory array, comprising,

a substrate;

a plurality of levels of memory cells formed on the substrate one level upon the other, the memory cells of each level are substantially aligned with memory cells in the adjacent level;

a plurality of sets of first select lines formed in each of the plurality of levels of memory cells substantially parallel to the substrate;

a plurality of sets of second select lines formed in planes orthogonal to the substrate; and

at least one switching element disposed on top of at least one of the plurality of second select lines

wherein each of the memory cells is adjacent to a respective first and second select line.

2. The cubic memory array of claim 1, wherein at least one of the memory cells stores multiple states allowing for more than one bit of information in the memory cell.

3. The cubic memory array of claim 1, wherein at least one of the memory cells includes an antifuse device.

4. The cubic memory array of claim 1, wherein at least one of the memory cells includes a tunnel junction device.

5. The cubic memory array of claim 1, wherein at least one of the memory cells includes,

a storage device having a first cross-sectional area;

a control element in series with the storage device and having a second cross-sectional area greater than the first cross-sectional area.

6. The cubic memory array of claim 1, wherein the plurality of sets of second select lines are formed of tungsten.

7. The cubic memory array of claim 1, wherein at least one of the memory cells includes an angled storage element patterned to create an enhanced electric field.

8. The cubic memory array of claim 1, wherein at least one of the memory cells has dual storage elements and wherein only one storage element is used.

9. The cubic memory array of claim 1, wherein the plurality of sets of first select lines are formed in at least a partial serpentine pattern.

10. The cubic memory array of claim 1, where at least one of the plurality of sets of second select lines are formed from an array of sub-pillars connected by a subset of second select lines formed parallel to the substrate surface.

11. A cubic memory array, comprising:

a substrate;

a first plane of an array of memory cells disposed on the substrate;

a first set of select lines forming rows of memory cells on the first plane;

a second plane of an array of memory cells disposed on the first plane and aligned with the array of memory cells of the first plane;

a second set of select lines orthogonal to the planer surface interconnecting the first and second planes of memory cells wherein each memory cell is adjacent to one of the first set of select lines and adjacent to one of the orthogonal second set of select lines; and

at least one switching element disposed on top of one of the second set of select lines.

12. The cubic memory array of claim 11, wherein at least one of the memory cells stores multiple states allowing for more than one bit of information in the memory cell.

13. The cubic memory array of claim 11, wherein at least one of the memory cells includes an antifuse device.

14. The cubic memory array of claim 11, wherein at least one of the memory cells includes a tunnel junction device.

15. The cubic memory array of claim 11, wherein at least one of the memory cells includes,

a storage device having a first cross-sectional area;

a control element in series with the storage device and having a second cross-sectional area greater than the first cross-sectional area.

16. The cubic memory array of claim 11, wherein the second set of select lines are formed of tungsten.

17. The cubic memory array of claim 11, wherein at least one of the memory cells includes an angled storage element patterned to create an enhanced electric field.

18. The cubic memory array of claim 11, wherein at least one of the memory cells has dual storage elements and wherein only one storage element is used.

19. The cubic memory array of claim 11, wherein the first set of select lines are formed in at least a partial serpentine pattern.

20. The cubic memory array of claim 11, wherein at least one of the second set of select lines are formed from an array of sub-pillars connected by a subset of second select lines formed parallel to the substrate surface.

21. A cubic memory array, comprising:

a plurality of horizontal select lines;

a plurality of vertical select lines;

a plurality of memory cells, each memory cell adjacent to a horizontal select line and adjacent to a vertical select line; and

at least one switching element disposed on top of at least one of the plurality of vertical select lines;

wherein the plurality of memory cells are arranged to form planes of horizontal select lines and planes of vertical select lines orthogonal to each other.

22. The cubic memory array of claim 21, wherein at least one of the memory cells stores multiple states allowing for more than one bit of information in the memory cell.

23. The cubic memory array of claim 21, wherein at least one of the memory cells includes an antifuse device.

24. The cubic memory array of claim 21, wherein at least one of the memory cells includes a tunnel junction device.

25. The cubic memory array of claim 21, wherein at least one of the memory cells includes,

a storage device having a first cross-sectional area;

a control element in series with the storage device and having a second cross-sectional area greater than the first cross-sectional area.

26. The cubic memory array of claim 21, wherein the vertical select lines are formed of tungsten.

27. The cubic memory array of claim 21, wherein at least one of the memory cells includes an angled storage element patterned to create an enhanced electric field.

28. The cubic memory array of claim 21, wherein at least one of the memory cells has dual storage elements and wherein only one storage element is used.

29. The cubic memory array of claim 21, wherein the horizontal of select lines are formed in at least a partial serpentine pattern.

30. The cubic memory array of claim 21, where at least one of the vertical select lines are formed from an array of sub-pillars connected by a subset of second horizontal select lines.

31. A cubic memory array, comprising:

a substrate having a first surface

a horizontal line disposed parallel to first surface of the substrate;

an isolation layer formed on a portion of the horizontal bit line;

a vertical bit line formed next to the isolation layer and contacting the horizontal bit line;

a switching element disposed on top of the vertical bit line;

a first memory cell having,

a storage element adjacent to the vertical bit line,

a control element in series with the storage element, and

a first horizontal word line disposed on the isolation layer and contacting the control element; and

at least one additional memory cell having a second horizontal word line disposed on the first memory cell and contacting the vertical bit line.

32. The cubic memory array of claim 31, wherein at least one of the storage elements stores multiple states allowing for more than one bit of information in the storage element.

33. The cubic memory array of claim 31, wherein at least one of the storage elements is an antifuse device.

34. The cubic memory array of claim 31, wherein at least one of the storage cells is a tunnel junction device.

35. The cubic memory array of claim 31, wherein

the storage device has a first cross-sectional area;

the control element has a second cross-sectional area greater than the first cross-sectional area.

36. The cubic memory array of claim 31, wherein the vertical bit line comprises tungsten.

37. The cubic memory array of claim 31, wherein the storage element comprises an angled storage element patterned to create an enhanced electric field.

38. The cubic memory array of claim 31, wherein the memory cells has an additional storage element and wherein the additional storage element is not used to store information.

39. The cubic memory array of claim 31, wherein the horizontal bit line is formed in at least a partial serpentine pattern.

40. The cubic memory array of claim 31, where the vertical bit line is formed from an array of sub-pillars connected by a subset of second horizontal bit lines.

41. A cubic memory array, comprising:

a plurality of horizontal word lines formed in a plurality of layers;

a plurality stacked memory cells, each memory cell disposed on one of the plurality of horizontal word lines;

a plurality of horizontal too sub-column connects;

a plurality of horizontal bottom sub-column connects;

a plurality of vertical bit lines contacting the plurality of stacked memory cells, wherein the vertical bit lines are formed in more than one pillar and are interconnected by one of the plurality of too sub-column connects and one of the plurality of bottom sub-column connects, wherein the every other pillar is connected to one of a too sub-column connect or a bottom sub-column connect.

42. The cubic memory array of claim 41, wherein at least one of the stacked memory cells includes a storage element that stores multiple states allowing for more than one bit of information in the storage element.

43. The cubic memory array of claim 41, wherein at least one of the stacked memory cells comprises an antifuse device.

44. The cubic memory array of claim 41, wherein at least one of the stacked memory cells comprises a tunnel junction device.

45. The cubic memory array of claim 41, wherein at least one of the stacked memory cells comprises,

a storage device having a first cross-sectional area;

a control element having a second cross-sectional area greater than the first cross-sectional area.

46. The cubic memory array of claim 41, wherein at least one of the plurality of vertical bit lines comprises tungsten.

47. The cubic memory array of claim 41, wherein at least one of the stacked memory storage cells comprises an angled storage element patterned to create an enhanced electric field.

48. The cubic memory array of claim 41, wherein the stacked memory cells has an additional storage element and wherein the additional storage element is not used.

49. The cubic memory array of claim 41, wherein one of the plurality of horizontal word lines is formed in at least a partial serpentine pattern.

50. A cubic memory array, comprising

control circuitry;

a first horizontal select line;

a first set of memory cells adjacent to the first horizontal select line;

a first set of vertical select lines intersecting with the first set of memory cells;

a second horizontal select line isolated from the first set of memory cells;

a second set of memory cells adjacent to the second horizontal select line;

a second set of vertical select lines intersecting with the second set of memory cells;

switching elements disposed on top of the vertical select lines;

a set of horizontal bitlines connecting the switching elements to the control circuitry;

a third horizontal select line isolated from and stacked upon the first horizontal select line;

a third set of memory cells adjacent to the third horizontal select line;

a fourth horizontal select line isolated from and stacked upon the second horizontal select line; and

a forth set of memory cells adjacent to the fourth horizontal select line;

wherein the first set of vertical select lines intersect with the third set of memory cells, and the second set of vertical select lines intersect with the fourth set of memory cells.

51. The cubic memory array of claim 50, wherein at least one of the memory cells includes a storage element that stores multiple states allowing for more than one bit of information in the storage element.

52. The cubic memory array of claim 50, wherein at least one of the memory cells comprises an antifuse device.

53. The cubic memory array of claim 50, wherein at least one of the memory cells comprises a tunnel junction device.

54. The cubic memory array of claim 50, wherein at least one of the memory cells comprises,

a storage device having a first cross-sectional area;

a control element having a second cross-sectional area greater than the first cross-sectional area.

55. The cubic memory array of claim 50, wherein at least one of the vertical select lines comprises tungsten.

56. The cubic memory array of claim 50, wherein at least one of the memory storage cells comprises an angled storage element patterned to create an enhanced electric field.

57. The cubic memory array of claim 50, wherein the memory cells has an additional storage element and wherein the additional storage element is not used.

58. A cubic memory array, comprising:

a substrate;

a set of horizontal word lines formed parallel to the substrate in a plurality of layers;

a set of top sub-column connects;

a set of bottom sub-column connects, the top and bottom sub-column connects parallel to the substrate and orthogonal to the set of horizontal word lines;

a set of vertical bitlines wherein the vertical bit lines are formed in more than one pillar and are interconnected by one of the set of top sub-column connects and one of the set of bottom sub-column connects;

wherein the every other pillar is connected to one of a top sub-column connect or a bottom sub-column connect; and

a set of memory cells, each memory cell having,

a storage element adjacent to a pillar,

a control element in series with the storage element connected to a horizontal word line.

59. The cubic array of claim 58, further comprising:

control circuitry having switching elements formed in the substrate;

a set of horizontal bit lines, each interconnected to every other pillar using the switching elements to select a desired pillar.

60. The cubic memory array of claim 58, wherein at least one of the storage elements stores multiple states allowing for more than one bit of information in the storage element.

61. The cubic memory array of claim 58, wherein at least one of the storage elements is an antifuse device.

62. The cubic memory array of claim 58, wherein at least one of the storage cells is a tunnel junction device.

63. The cubic memory array of claim 58, wherein

the storage device has a first cross-sectional area;

the control element has a second cross-sectional area greater than the first cross-sectional area.

64. The cubic memory array of claim 58, wherein the vertical bit line comprises tungsten.

65. The cubic memory array of claim 58, wherein the storage element comprises an angled storage element patterned to create an enhanced electric field.

66. The cubic memory array of claim 58, wherein the memory cells has an additional storage element and wherein the additional storage element is not used to store information.

67. The cubic memory array of claim 58, wherein the horizontal word line is formed in at least a partial serpentine pattern.