High voltage row and column driver for programmable resistance memory
First Claim
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1. A memory system, comprising:
- a programmable resistance memory cell coupled to a column line and a row line; and
a driver circuit having an output node for outputting an output voltage to the column line or the row line, the driver circuit comprising;
a plurality of PMOS transistors coupled in series between said output node and a first node of said driver circuit, and a plurality of NMOS transistors coupled is series between said output node and a second node of said driver circuit.
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Abstract
A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.
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Citations
44 Claims
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1. A memory system, comprising:
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a programmable resistance memory cell coupled to a column line and a row line; and
a driver circuit having an output node for outputting an output voltage to the column line or the row line, the driver circuit comprising;
a plurality of PMOS transistors coupled in series between said output node and a first node of said driver circuit, and a plurality of NMOS transistors coupled is series between said output node and a second node of said driver circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
20.The memory system of claim 1, wherein said driver circuit is adapted so that the maximum magnitude of said output voltage is greater than the maximum magnitude of the voltage across the drain and source of each of said NMOS transistors and each of said PMOS transistors.
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20. A memory system, comprising:
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a programmable resistance memory cell coupled to a column line and a row line; and
a driver circuit having an output node for outputting an output voltage to the column line or the row line, the driver circuit comprising;
a plurality of PMOS transistors coupled in series, and a plurality of NMOS transistors coupled is series, said plurality of PMOS transistors being coupled in series with said plurality of NMOS at said output node.
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- 21. The memory system of claim 21, further comprising a control circuit including a first additional PMOS transistor coupled in series with a second additional PMOS transistor, said control circuit outputting a control voltage to a gate at least one of said plurality of PMOS transistors.
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24. The memory system of claim 24, further comprising a switching circuit selectively coupling a second voltage to said output node.
- 25. The memory system of claim 25, wherein said second voltage is a power supply voltage, said first voltage being greater than said power supply voltage.
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28. The memory system of claim 28, wherein a gate of said second PMOS transistor and a gate of said first NMOS transistor are coupled to a second voltage.
- 29. The memory system of claim 29, further comprising a third PMOS transistor and a fourth PMOS transistor coupled in series at a connection point, said connection point coupled to a gate of said first PMOS transistor.
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30. The memory system of claim 30, wherein a gate of said third PMOS transistor and a gate of said fourth PMOS transistor are coupled to said second voltage.
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32. The memory system of claim 32, wherein said first voltage is greater than said power supply voltage.
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33. The memory system of claim 33, wherein said first voltage is less than or equal to said power supply voltage multiplied by two.
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35. The memory system of claim 35, wherein said switching circuit comprises a fifth PMOS transistor coupled in series with a third NMOS transistor.
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36. The memory system of claim 36, wherein a source of said fifth PMOS transistor is coupled to said first node, a drain of said fifth PMOS transistor is coupled to a drain of said third NMOS transistor, a source of said third NMOS transistor is coupled to said output node.
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39. A memory system, comprising:
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a programmable resistance memory cell coupled to a column line and a row line; and
a driver circuit having at least two MOS transistors of the same type coupled in series between a first node and an output node, said driver circuit outputting an output voltage from said output node to the column line or the row line, said driver circuit adapted so that the maximum magnitude of said output voltage is greater than the maximum magnitude of the voltage across the drain and source of each of said at least two MOS transistors.
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Specification