Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells

• US 6,781,877 B2
• Filed: 09/06/2002
• Issued: 08/24/2004
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian, Li, Yan, Fong, Yupin, Chen, Jian, Quader, Khandker N.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/237,426
• Publication Number:
  US 20040047182A1
• Time in Patent Office: 718 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.28, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

Claims

1. A method of operating an array of non-volatile memory cells that store data as different levels of charge in charge storage elements thereof, wherein adjacent groups of the charge storage elements have field coupling therebetween, comprising:

programming data into a first of the groups of charge storage elements with a first set of storage levels along with an indication that the first set of storage levels has been used,

thereafter programming data into a second of the groups of charge storage elements with the first set of storage levels along with an indication that the first set of storage levels has been used, and

thereafter increasing the charge levels of the first of the groups of charge storage elements from the first set of storage levels to a second set of storage levels and storing an indication that the second set of storage levels has been used.

2. The method of claim 1, wherein the adjacent groups of charge storage elements are positioned in adjacent rows of memory cells.

3. The method of claim 1, wherein the charge storage elements are conductive floating gates.

4. The method of claim 1, wherein the first and second sets of storage levels each include more than two storage levels, thereby to store more than one bit of data in the individual storage elements.

5. A method of operating a memory cell array having at least first and second groups of memory cells, wherein the first and second groups have electric field coupling therebetween, comprising:

programming data into the first group of memory cells with a first set of threshold verify levels, including storing an indication that the first set of threshold levels has been utilized,

thereafter programming data into the second group of memory cells with the first set of threshold verify levels, including storing an indication that the first set of threshold levels has been utilized,

thereafter reading the data programmed into the first group of memory cells and said indication with a first set of read levels, and

thereafter re-programming the read data into the first group with a second set of threshold verify levels, including storing an indication that the second set of threshold levels has been utilized, the second set of threshold verify levels being higher than the first set of threshold verify levels,

wherein data is readable from the first group with a second set of read levels that is higher than the first set of read levels.

6. The method of claim 5, additionally comprising:

reading data stored in the second group of memory cells with the second set of read levels, including the indication that the first set of threshold levels has been utilized during programming, and

in response to reading that the first set of threshold levels has been utilized during programming, re-reading data stored in the second group of memory cells with the first set of read levels.

7. The method of claim 6, wherein the adjacent groups of memory cells are positioned in adjacent rows of memory cells.

8. The method of claim 6, wherein the memory cells individually include at least one charge storage element that is programmed with the data.

9. The method of claim 8, wherein the charge storage elements are conductive floating gates.

10. The method of claim 6, wherein the first and second sets of threshold verify levels each include more than two levels, thereby to store more than one bit of data in the individual memory cells.

11. A method of programming non-volatile memory cells of a type that store data as different levels of charge in charge storage elements thereof, wherein the charge storage elements are arranged in at least first, second and third rows in sequence across an array of cells with the storage elements of at least those rows immediately adjacent each other having field coupling therebetween, comprising in the order stated:

programming the charge storage elements of the second row to first levels that are less than the data storage levels,

increasing the charge levels on the charge storage elements of the first row from less than the data storage levels and up to the data storage levels,

programming the charge storage elements of the third row to first levels that are less than the data storage levels, and

increasing the charge levels on the charge storage elements of the second row from less than the data storage levels and up to the data storage levels.

12. The method of claim 11, wherein increasing the charge levels on the charge storage elements of the first and second rows each includes:

reading the data stored in the first or second row, and

programming the memory cells of the first or second row with the data read therefrom to the data storage charge levels.

13. The method of claim 12, wherein increasing the charge levels on the charge storage elements of the first and second rows is each accomplished without erasing the data stored in the first or second row.

14. A method of operating an array of non-volatile memory cells that store data as different levels of charge in charge storage elements thereof, wherein charge storage elements of adjacent groups are capacitively coupled with each other, comprising:

initially programming data into the individual groups of charge storage elements with a first set of storage levels along with an indication that the first set of storage levels has been used,

thereafter increasing the charge levels of the individual groups of charge storage elements from the first set of storage levels to a second set of storage levels and storing an indication that the second set of storage levels has been used,

initially reading the individual groups of charge storage elements including said indication with reading levels corresponding to use of the second set of storage levels, and

if the indication is initially read that the first set of storage levels has been used, re-reading the individual groups of charge storage elements with reading levels corresponding to use of the first set of storage levels.

15. The method of claim 14, wherein increasing the charge levels on the individual groups of charge storage elements includes:

reading the data stored in the individual groups of charge storage elements, and

programming the memory cells of the individual groups from which the data has been read.

16. The method of claim 14, wherein increasing the charge levels on the individual groups of charge storage elements includes doing so without erasing the data stored in the first or second row.

17. The method of claim 14, wherein the adjacent groups of charge storage elements include adjacent rows of memory cells.

18. The method of claim 14, wherein the charge storage elements are conductive floating gates.

19. The method of claim 14, wherein the first and second sets of storage levels each include more than two storage levels, thereby to store more than one bit of data in the individual storage elements.