Non-volatile memory erase circuitry
First Claim
Patent Images
1. A non-volatile memory device comprising:
- an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells;
a voltage pump circuit to generate an elevated voltage output from an input voltage; and
control circuitry to increase or decrease, during erase and program operations, a current sourced by the voltage pump circuit in response to an output of the counter circuit.
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Abstract
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.
11 Citations
17 Claims
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1. A non-volatile memory device comprising:
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an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells;
a voltage pump circuit to generate an elevated voltage output from an input voltage; and
control circuitry to increase or decrease, during erase and program operations, a current sourced by the voltage pump circuit in response to an output of the counter circuit.- View Dependent Claims (2, 3, 4)
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5. A flash memory device comprising:
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an array of floating gate memory cells;
a first voltage pump coupled to produce an output voltage from an input voltage, wherein the output voltage is produced by sequentially elevating the input voltage through first series coupled pump stages;
a second voltage pump coupled in parallel to the first voltage pump to produce the output voltage from the input voltage, wherein the output voltage is produced by sequentially elevating the input voltage through second series coupled pump stages;
a counter to maintain a running count of voltage pulses applied to the array during erase and program operations; and
control circuitry coupled to the first and second voltage pumps and the counter, wherein the control circuit selectively activates, during erase and program operations, the first and second voltage pumps in response to the running count of the counter. - View Dependent Claims (6)
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7. A flash memory device comprising:
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an array of floating gate memory cells;
control circuitry to perform an erase operation on the floating gate memory cells, wherein the floating gate memory cells are erased by applying voltage pulses to the floating gate memory cells and a current limit of the voltage pulses is increased or decreased based upon a number of prior voltage pulses applied to the floating gate memory cells and a counter to generate the number of prior voltage pulses. - View Dependent Claims (8)
a first and second parallel voltage pumps each coupled to produce an output voltage from an input voltage, wherein the output voltage is produced by sequentially elevating the input voltage through series coupled pump stages;
a counter to maintain a running count of voltage pulses applied to the array during erase and program operations, wherein the control circuitry is coupled to the first and second parallel voltage pumps and the counter to selectively activate the first and second parallel voltage pumps in response to the running count of the counter.
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9. A method of erasing a flash memory device comprising:
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pre-programming a block of memory cells;
generating an erase voltage from a supply voltage using a voltage pump circuit having a plurality of parallel coupled pumps;
applying a plurality of erase pulses to the block of memory cells;
counting the erase voltage pulses applied to the memory; and
adjusting a current limit of the erase voltage by selectively activating the plurality of parallel coupled pumps in response to the counted erase voltage pulses. - View Dependent Claims (10, 11)
activating a first plurality of pumps of the voltage pump circuit while an output count of a counter circuit is equal to or less than X counts, such that the pump circuit provides an output voltage with a first current limit; and
activating the first plurality of pumps and a second plurality of pumps of the voltage pump circuit while an output count of the counter circuit is greater than X counts, such that the pump circuit provides the output voltage with a second current limit that is greater than the first current limit.
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12. A non-volatile memory device comprising:
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an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells;
a voltage pump circuit having a plurality of voltage pumps to generate an elevated voltage output from an input voltage; and
control circuitry to selectively activate each of the plurality of voltage pumps, during erase and program operations, to adjust a current sourced by the voltage pump circuit in response to an output of the counter circuit.
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13. A non-volatile memory device comprising:
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an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells;
a voltage pump circuit having a plurality of parallel voltage pumps to generate an elevated voltage output from an input voltage; and
control circuitry to selectively activate each of the plurality of voltage pumps, during erase and program operations, to adjust a current sourced by the voltage pump circuit in response to an output of the counter circuit, wherein a number of activated parallel pumps increases in response to a corresponding count increase of the output of the counter circuit. - View Dependent Claims (14, 15, 16, 17)
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Specification