Anti-fuse structure and method of writing and reading in integrated circuits

• US 6,781,887 B2
• Filed: 06/05/2003
• Issued: 08/24/2004
• Est. Priority Date: 06/02/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gelsomini, Tito, San, Kemal Tamer
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/455,579
• Publication Number:
  US 20030207526A1
• Time in Patent Office: 446 Days
• Field of Search: 365/189.01, 365/189.12
• US Class Current: 365/189.16
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Claims

1. A method for encoding data into the write-register of an integrated circuit having a plurality of components including a gate-controlled insulator over an isolated p-well, comprising the steps of:

applying an overstress voltage pulse between said component gate and said isolated p-well, thereby locally inverting the insulating character of said gate insulator, to permanently encode binary data into said write-register; and

controlling said pulses by superposing a write-enable pulse of predetermined polarity and duration with a p-well pulse of opposite polarity and shorter duration.

2. The method according to claim 1 wherein the step of controlling said pulses by superposing said write-enable pulse and said p-well pulse includes the steps of:

loading the data, to be encoded in said write-register, into the shift register associated with said write-register;

initiating the write-enable voltage pulse by increasing the power supply voltage to a predetermined value;

after a time delay of about 1 μ

s, initiating directly from the user said p-well voltage pulse, said p-well pulse having a polarity opposite to the polarity of said write-enable voltage pulse and a magnitude such that the absolute voltage sum of said p-well pulse and said write-enable pulse is sufficient to locally invert the insulating character of said gate insulator;

after a time duration sufficient to locally invert said insulating character to electrical conductivity, discontinuing said p-well pulse; and

after a delay of about 1 μ

s, discontinuing said write-enable pulse.

3. The method according to claim 1 wherein locally inverting said gate insulator by an overstress voltage pulse encodes the first binary digit as a “

logic 0”

in said component.

4. The method according to claim 1 wherein preserving said insulating character of said gate insulator encodes the second binary digit as a “

logic 1”

in said component.

5. The method according to claim 1 wherein said overstress pulses are applied while said integrated circuit is still portion of a semiconductor wafer.

6. The method according to claim 1 wherein said overstress pulses are also applied after said integrated circuit has been singulated from said wafer, assembled and packaged.