Memory having variable refresh control and method therefor
First Claim
1. A memory comprising:
- a plurality of memory cells that require periodic refreshing to maintain stored data;
a charge pump, coupled to the plurality of memory cells, for providing a substrate bias;
a voltage regulator, coupled to the charge pump, for providing a pump enable signal for controlling a voltage level of the substrate bias;
a refresh counter having an input terminal coupled to the voltage regulator for receiving the pump enable signal, and in response, providing a refresh timing signal; and
a refresh control circuit, coupled to receive the refresh timing signal, and in response, controlling refresh operations of the plurality of memory cells.
22 Assignments
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Accused Products
Abstract
A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.
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Citations
20 Claims
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1. A memory comprising:
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a plurality of memory cells that require periodic refreshing to maintain stored data;
a charge pump, coupled to the plurality of memory cells, for providing a substrate bias;
a voltage regulator, coupled to the charge pump, for providing a pump enable signal for controlling a voltage level of the substrate bias;
a refresh counter having an input terminal coupled to the voltage regulator for receiving the pump enable signal, and in response, providing a refresh timing signal; and
a refresh control circuit, coupled to receive the refresh timing signal, and in response, controlling refresh operations of the plurality of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory comprising:
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a plurality of memory cells that require periodic refreshing to maintain stored data;
a charge pump for providing a substrate bias to the plurality of memory cells;
a voltage regulator, coupled to the charge pump, for providing a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits;
a refresh control circuit for controlling refresh operations of the plurality of memory cells; and
a refresh counter having an input terminal coupled to the voltage regulator for receiving the pump enable signal, and in response, providing a refresh timing signal to the refresh control circuit to control a refresh rate of the plurality of memory cells;
wherein the refresh rate is adjusted by the refresh counter in response to the voltage regulator asserting the pump enable signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification