Flash memory having a flexible bank partition

• US 6,781,914 B2
• Filed: 08/23/2001
• Issued: 08/24/2004
• Est. Priority Date: 08/23/2001
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Ha, Chang Wan
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US09/938,410
• Publication Number:
  US 20030039140A1
• Time in Patent Office: 1,097 Days
• Field of Search: 365/230.03, 365/63, 365/189.04, 365/185.11, 365/185.33, 365/185.01
• US Class Current: 365/230.03
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification

Abstract

A simultaneous operation flash memory chip architecture having a flexible memory bank partition for forming first and second memory banks from a plurality of flash memory arrays, said partition being defined by selecting one of a plurality of preformed metal masks, which allows the formation and extension of pre-decoded address lines to inputs of decoders associated with the first and second memory banks, respectively.

Claims

1. An integrated circuit memory comprising:

a plurality of memory arrays partitioned into first and second memory banks in correspondence with one of a plurality of mask options such that the length of a plurality of bit lines in each of the first and second memory banks remains fixed for all of the plurality of mask options, wherein for each of the plurality of mask options the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays.

2. The integrated circuit memory of claim 1 wherein each of the plurality of mask options corresponds to a different partitioning of the memory arrays into the first and second memory banks.

3. The integrated circuit memory of claim 1 wherein memory operations can be carried out simultaneously in the first and second memory banks.

4. The integrated circuit memory of claim 1 wherein each of the memory arrays in the first and second memory banks has substantially the same number of memory cells.

5. The integrated circuit memory of claim 1 wherein each of the plurality of memory arrays includes a plurality of memory cells arranged along rows and columns, the integrated circuit memory further comprising:

column selection circuit coupled to select columns of cells in response to column addresses; and

row selection circuit coupled to select rows of cells in response to row addresses,

wherein each of the plurality of mask options configures the row and column selection circuits to obtain a different partitioning of the plurality of memory arrays into the first and second memory banks.

6. The integrated circuit memory of claim 5 wherein the row and column selection circuits respectively receive a first row address and a first column address for accessing one or more memory cells in the first memory bank, and the row and column selection circuits respectively receive a second row address and a second column address for accessing one or more memory cells in the second memory bank.

7. The integrated circuit memory of claim 1 wherein the integrated circuit memory receives a first bank address and a second bank address, the first bank address including row and column addresses for accessing one or more memory cells in the first memory bank, and the second bank address including row and column addresses for accessing one or more memory cells in the second memory bank.

8. The integrated circuit memory of claim 1 wherein the one of a plurality of mask options is used to form a metal layer in the integrated circuit.

9. An integrated circuit memory comprising:

a plurality of memory arrays each having memory cells arranged along rows and columns; and

reconfigurable row and column selection circuits coupled to access memory cells in the plurality of memory arrays in response to row and column addresses,

wherein one of a plurality of metal mask options is selected to configure the row and column selection circuits to obtain a desired partitioning of the plurality of memory arrays into first and second memory banks such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays, and

wherein memory operations can be carried out simultaneously in the first and second memory banks.

10. The integrated circuit memory of claim 9 wherein each of the plurality of metal mask options corresponds to a different partitioning of the memory arrays into the first and second memory banks.

11. The integrated circuit memory of claim 9 wherein the integrated circuit memory receives a first bank address and a second bank address, the first bank address including row and column addresses for accessing one or more memory cells in the first memory bank, and the second bank address including row and column addresses for accessing one or more memory cells in the second memory bank.

12. An integrated circuit memory comprising:

a plurality of memory arrays each having memory cells arranged along rows and columns; and

reconfigurable row and column selection circuits coupled to access memory cells in the plurality of memory arrays in response to row and column addresses,

wherein the plurality of memory arrays are partitioned, into first and second memory banks by configuring the row and column selection circuits into one of a plurality of mask-selectable configurations such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays,

wherein each of the mask-selectable configurations corresponds to one of a plurality of metal masks used to form a metal layer in the integrated circuit.

13. A method of configuring an integrated circuit memory having a plurality of memory arrays, the method comprising:

partitioning the plurality of memory arrays into first and second memory banks by selecting one of a plurality of mask options such that the length of a plurality of bit lines in each of the first and second memory banks remains fixed for all of the plurality of mask options, wherein for each of the plurality of mask options the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays.

14. The method of claim 13 wherein each of the plurality of memory arrays includes a plurality of memory cells arranged along rows and columns, and the integrated circuit memory includes row and column selection circuits coupled to select memory cells in the plurality of memory arrays,

wherein the plurality of memory arrays are partitioned into first and second memory banks by configuring the row and column selection circuits into one of a plurality of mask-selectable configurations, each of the mask-selectable configurations corresponding to one of the plurality of mask options.

15. The method of claim 13 wherein each of the plurality of mask options corresponds to a different partitioning of the memory arrays into the first and second memory banks.

16. The method of claim 13 wherein memory operations can be carried out simultaneously in the first and second memory banks.

17. A method of manufacturing an integrated circuit memory having row and column selection circuits coupled to a plurality of memory arrays, the method comprising:

applying one of a plurality of metal masks to form a metal layer and to configure the row and column select circuits to obtain a desired partitioning of the plurality of memory arrays into first and second memory banks such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays,

wherein each of the plurality of metal masks corresponds to a different configuration of the row and column selection circuits, and each of the different configurations of the row and column selection circuits correspond to a different partitioning of the plurality of memory arrays into the first and second memory banks.