PLL lockout watchdog

• US 6,782,068 B1
• Filed: 06/30/2000
• Issued: 08/24/2004
• Est. Priority Date: 06/30/2000
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wilson, James E., Cowe, Tomasz
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WANG, TED M
• Application Number:
  US09/608,753
• Time in Patent Office: 1,516 Days
• Field of Search: 375/376, 375/136, 375/137, 375/354, 375/355, 375/327, 375/373, 375/351, 371/62, 331/11, 331/1.A, 327/156
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence

Abstract

A circuit that may be configured to detect a lockout condition of a phase lock loop (PLL) circuit. The circuit may be configured to forcibly correct an operating frequency of the PLL circuit.

Claims

1. A circuit configured to detect a lockout condition of a phase lock loop (PLL) circuit, wherein (A) said circuit is configured to forcibly correct an operating frequency of the PLL circuit by (i) switching to a normal path comprising a feedback of said operating frequency when said lockout condition is not detected and (ii) switching to a recovery path, separate from said feedback of said operating frequency, when said lockout condition is detected and (B) said circuit comprises a first counter configured to (a) count an output reference frequency and (b) initiate a reset of said circuit.

2. The circuit according to claim 1, wherein said recovery path receives a reference frequency.

3. The circuit according to claim 1, wherein said recovery path comprises a first frequency higher than a second frequency of said normal path.

4. The circuit according to claim 1, wherein said circuit comprises a PLL lockout watchdog circuit.

5. The circuit according to claim 1, further configured to switch between a first and a second feedback path.

6. The circuit according to claim 5, further configured in response to an output of said PLL circuit.

7. The circuit according to claim 6, wherein said output initiates a reset of said circuit.

8. The circuit according to claim 1, further configured in response to a control voltage signal.

9. The circuit according to claim 8, further configured to control a voltage level of said control voltage signal.

10. The circuit according to claim 1, further configured in response to a reference frequency.

11. The circuit according to claim 1, further comprising:

a second counter configured to count an input reference frequency and initiate a lockout condition.

13. The method according to claim 1, wherein said recovery path receives a reference frequency.

12. A method for detecting a lockout condition comprising the steps of:

(A) detecting a lockout condition of a phase lock loop (PLL) circuit;

(B) forcibly correcting an operating frequency of the PLL by (i) switching to a normal path comprising a feedback of said operating frequency when said lockout condition is not detected and (ii) switching to a recovery path, separate from said feedback of said operating frequency, when said lockout condition is detected; and

(C) counting an output reference frequency to initiate a reset of said PLL.

14. An apparatus comprising:

means for detecting a lockout condition of a phase lock loop (PLL) circuit;

means for correcting an operating frequency of the PLL circuit by (i) switching to a normal path comprising a feedback of said operating frequency when said lockout condition is not detected and (ii) switching to a recovery path, separate from said feedback of said operating frequency, when said lockout condition is detected; and

means for (a) counting an output reference frequency and (b) initiating a reset of said apparatus.