Optimized configurable scheme for demand based resource sharing of request queues in a cache controller

• US 6,782,455 B2
• Filed: 05/23/2002
• Issued: 08/24/2004
• Est. Priority Date: 06/30/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mosur, Lokpraveen B., Palanca, Salvador
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US10/155,522
• Publication Number:
  US 20020178334A1
• Time in Patent Office: 824 Days
• Field of Search: 711/100, 711/118, 711/133, 711/143, 711/151, 711/154, 711/158
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A cache controller is presented having at least one register. The cache controller is connected to a cache memory, which is connected to the register. The cache controller dynamically selects between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority. Also presented is a device having a single request queue and a corresponding single set of buffers. The device dynamically selects between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority.

Claims

1. A method comprising

detecting a core request;

detecting a writeback request;

prioritizing the writeback entry and an incoming core request;

determining if any entries are available in a cache controller;

allocating a first entry for a writeback eviction;

allocating an entry for the incoming core request if a second entry is available;

redispatching the incoming core request if no additional entries are available;

determining status of a register bit within a register capable of being one of set and cleared, and

dynamically selecting between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority based on said determined status of said register bit.

2. The method of claim 1, further comprising prioritizing writeback evictions and incoming core requests, wherein a higher priority is given to writeback evictions over incoming core requests.

3. The method of claim 1, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of writeback evictions and core requests.

4. A computer system comprising:

at least one computer processor, the computer processor having at least one cache memory and a cache controller;

a register coupled to the at least one processor;

a memory bus coupled to the at least one computer processor;

a memory coupled to the memory bus; and

a means for dynamically selecting between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority, said means comprising a register bit within the register capable of being one of set and cleared, wherein the computer processor queries the register to determine if the register bit is one of set and cleared.

5. The computer system of claim 4, wherein a higher priority is given to writeback evictions over incoming core requests.

6. The computer system of claim 4, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of a writeback eviction requests and core requests.

7. A computer system comprising:

at least one computer processor, the computer processor having at least one cache memory and a cache controller;

a register coupled to the at least one processor;

a memory bus coupled to the at least one computer processor;

a memory coupled to the memory bus; and

a register bit within the register capable of being one of set and cleared,

wherein said cache controller dynamically selects between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority, and the computer processor queries the register to determine if the register bit is one of set and cleared.

8. The computer system of claim 7, wherein a higher priority is given to writeback evictions over incoming core requests.

9. The computer system of claim 7, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of a writeback eviction requests and core requests.

10. A cache controller comprising;

at least one register;

a cache memory coupled to said register, and

a register bit within the register capable of being one of set and cleared, wherein said cache controller dynamically selects between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority, and the cache controller queries the register to determine if the register bit is one of set and cleared.

11. The cache controller of claim 10, wherein a higher priority is given to writeback evictions over incoming core requests.

12. The cache controller of claim 10, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of a writeback eviction requests and core requests.

13. An apparatus comprising;

a single request queue and a corresponding single set of buffers, and

a register having a register bit capable of being one of set and cleared,

wherein said apparatus dynamically selects between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority, and the apparatus queries the register to determine if the register bit is one of set and cleared.

14. The apparatus of claim 13, further comprising:

a buffer in the corresponding single set of buffers, said buffer is capable of servicing one of writeback eviction requests and core requests.

15. The apparatus of claim 14, wherein a higher priority is given to writeback evictions over incoming core requests.