System for reducing test data volume in the testing of logic products

• US 6,782,501 B2
• Filed: 10/05/2001
• Issued: 08/24/2004
• Est. Priority Date: 01/23/2001
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ferko, Andrew, Distler, Frank O., Keller, Brion L., Farnsworth, L. Owen, Koenemann, Bernd K.
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US09/972,000
• Publication Number:
  US 20020099992A1
• Time in Patent Office: 1,054 Days
• Field of Search: 714/738, 714/741, 714/732, 714/726, 714/724, 714/734, 714/736, 714/728, 714/32, 714/33, 703/13, 703/14, 341/94
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.

Claims

1. A method for reducing test data volume in the testing of logic product under test, comprising the steps of:

(a) generating original test vector data including care bits and non-care bits;

(b) filling said non-care bits with a repeated value to form a highly compressible test vector data set;

(c) compressing said highly compressible test vector data set to form a compressed test vector data set;

(d) simulating the product under test with test input data to determine expected test response data generated from the product under test in response to the original test vector data;

(e) compressing the expected test response data into a compact error-detecting expected signature.

2. The method of claim 1, further comprising the steps of:

(f) transmitting said compressed test vector data set to a test system;

(g) recovering the care bits of said original test vector data from said compressed vector data set, for loading said original test vector data into input latches of a tester in said test system;

(h) compressing actual test response data from the product under test into a compact error-detecting actual signature; and

(i) comparing said error-detecting actual signature with said error-detecting expected signature for the test.

3. The method of claim 2 wherein said step (g) comprises:

decompressing said compressed test vector data set;

extracting a differential vector data set and attached header, said differential vector data set formed by XORing said care bits with corresponding bits in a background vector data set;

reconstructing said background vector data set from said header; and

XORing said reconstructed background vector data set with said extracted differential vector data set to form a reconstructed test vector data set.

4. The method of claim 3, wherein said reconstructed test vector data set comprises the care bits of the original test vector data, with the non-care bits having the values of the corresponding background vector data bits.

5. The method of claim 2 wherein said response data compression is performed by hardware in the product under test.

6. The method of claim 5 wherein said hardware implements an error-detecting Cyclic Redundacy Code generator.

7. The method of claim 2 wherein said response data compression is performed by hardware located between the product under test and the tester.

8. The method of claim 7 wherein said hardware implements an error-detecting Cyclic Redundacy Code generator.

9. The method of claim 2 wherein said response data compression is performed by hardware located inside the tester.

10. The method of claim 9 wherein said hardware implements an error-detecting Cyclic Redundacy Code generator.

11. The method of claim 2 wherein said response data compression is performed by software means located in the tester.

12. The method of claim 11 wherein said software means implement an error-detecting Cyclic Redundacy Code generator.

13. The method of claim 2 wherein said response data compression is performed by a software or hardware means, the software or hardware means is reset to a fixed, pre-determined value at the beginning of each test such that the said error-detecting actual signature obtained for the test is independent of the signatures from prior tests.

14. The method of claim 2 wherein said step (i) comprising the steps of:

(j) repeating one or more failing tests for which of said error-detecting actual signature is different from said error-detecting expected signature using the same test input stimulus data as used for creating said error-detecting actual signature; and

(k) unloading the test output response data for the said repeated failing tests to the tester without compressing said test output response data.

15. The method of claim 1, wherein said step (b) comprises:

generating a background vector data set; and

forming a differential vector data set by XORing said care bits with corresponding bits in said background vector data set.

16. The method of claim 15, wherein said XORing sets a substantial portion of said care bits to a value of 0 in said differential vector data set.

17. The method of claim 15, further comprising the step of attaching a header to said differential vector data set, said header identifying an algorithm and seed used to generate said background vector data set, wherein said differential vector data set with attached header form said highly compressible test vector data set.

18. The method of claim 15, wherein said background vector data set comprises a random distribution of bits having values of both “

0” and

“

1”

.