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Behavioral-synthesis electronic design automation tool business-to-business application service provider

  • US 6,782,511 B1
  • Filed: 05/25/2000
  • Issued: 08/24/2004
  • Est. Priority Date: 05/26/1999
  • Status: Expired due to Term
First Claim
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1. A business-to-business application service provider with a software tool environment offered on a pay-per-use basis for system-on-a-chip designers to create unique intellectual property and providing an on-demand electronic design automation (EDA) computer program hosted on an Internet website, comprising the steps of:

  • generating an electronic circuit design;

    partitioning said electronic circuit design into its constituent blocks and protocol design;

    coding said constituent blocks and protocol design in hardware description language (HDL);

    using high-level synthesis (HLS) for operation scheduling and resource allocation of said constituent blocks and protocol design;

    technology-independent Boolean optimizing said constituent blocks after operation scheduling and resource allocation to produce an intermediate design;

    technology-mapping said intermediate design to select particular devices for a hardware implementation of said electronic circuit design;

    placing said particular devices at locations in a semiconductor chip; and

    routing a set of interconnections of said particular devices;

    wherein, the stop of technology-mapping comprises the sub-steps of;

    partitioning an original circuit design into a set of corresponding logic trees;

    ordering said set of corresponding logic trees into an ordered linear list such that each tree-T that drives another ordered tree precedes said other ordered tree, and such that each ordered tree that drives said tree-T precedes said tree-T;

    sweeping forward in said ordered linear list while computing a set of Pareto-optimal load/arrival curves for each of a plurality of net nodes that match a technology-library element; and

    sweeping backward in said ordered linear list while using said set of Pareto-optimal load/arrival curves for each of said net nodes and a capacitive load to select a best one of said technology-library elements with a shortest signal arrival time;

    wherein, only net nodes that correspond to a gate input are considered, and any capacitive loads are predetermined.

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