Package structure and method for making the same

• US 6,784,020 B2
• Filed: 10/30/2002
• Issued: 08/31/2004
• Est. Priority Date: 10/30/2001
• Status: Expired due to Term

• Current Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Original Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Inventors: Huang, Yi-Mou, Lee, Chengkuo
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/283,129
• Publication Number:
  US 20040087043A1
• Time in Patent Office: 671 Days
• Field of Search: 438/106, 438/107, 438/112, 438/118, 438/119, 438/124, 438/126, 438/974, 438/975
• US Class Current: 438/106
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 7/0048 between the MEMS die and the substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 438/974 : Substrate surface preparation

Abstract

A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MFMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.

Claims

1. A method of making a package structure, comprising the steps of:

providing at least two substrates for composing the package structure;

making functional elements on at least one of the substrate;

assembling discrete elements, dies and devices onto at least one of the substrate;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said substrates;

making electrical conduction line and lead line on at least one of the substrate for further constructing electrical conduction and signal connection between two different substrates;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the substrate;

aligning and pre-bonding a substrate with the said interposers, micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, may accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely scaled interface between the pre-bonded interfaces of substrates by encapsulating the interfaces via through-hole microstructures, therefore a completely sealed package interface of each packaged devices or apparatus in the form of the said package is done and

separating each packaged structures, devices or apparatus in the form of the said package.

2. A method of making a package structure as claimed in claim 1, wherein the said substrates are materials of semiconductors, compound semiconductor, metals, plastics, polymers, ceramics and glasses.

3. A method of making a package structure as claimed in claim 1, wherein the said substrates are substrates of wafer form.

4. A method of making a package structure as claimed in claim 1, wherein the said function elements are microelectronics such as passive elements of resistors, capacitors and inductors;

optoelectronics of laser diodes, photo-detectors, photo-sensors;

microelectromechanical systems of micro-fluidic systems, micro-total-analysis systems, bio-medical devices, bio-chips, bio-sensors and micro-opto-electro-mechanical systems.

5. A method of making a package structure as claimed in claim 1, wherein the said assembled and integrated functional elements, dies and devices inside the said package structure comprise plural functions, such as, computing, sensing, actuating, adjusting and controlling;

then the said package structures are devices and apparatus in a format of system-in-a-package (SiP).

6. A method of making a package structure as claimed in claim 1, wherein the said assembled and integrated functional elements, dies and devices inside the said package structure comprise plural functions, such as, computing, sensing, actuating, adjusting and controlling;

wherein the said substrates are substrates of wafer form, then the said package structures are devices and apparatus in a format of wafer-level-system-in-a-package (WLSiP).

7. A method of making a package structure as claimed in claim 1, wherein the technologies for assembling discrete elements or dies or devices onto at least one of the substrate are solder bonding, eutectic bonding, adhesive bonding, wire bonding and flip-chip bonding.

8. A method of making a package structure as claimed in claim 1, wherein the said interposers, micro-joints and microstructures between the pre-bonded substrates can make a spatial spacing of interface of appropriate height, therefore a space formed due to the microstructures of this height can offer a room to accommodate the protruding microstructures such as assembled elements, dies and devices;

three dimensional micro-electro-mechanical structures of sensors, actuators, three dimensional opto-electronics elements and fluidic channels.

9. A method of making a package structure as claimed in claim 1, wherein cavities made on the substrates before the pre-bonding process can lead to a spatial room of appropriate height inside the said package structure after pre-bonding and encapsulating processes, therefore a space formed due to the cavities can offer a room to accommodate the protruding microstructures such as assembled elements, dies and devices;

three dimensional micro-electro-mechanical structures of sensors, actuators, three dimensional opto-electronics elements and fluidic channels, wherein the said cavities in a said substrate can have various heights.

10. A method of making a package structure as claimed in claim 1, wherein the formed interposers, micro-joints and microstructures for forming pre-bonding interface and connection between two substrates are eutectic metal structures, solder structures, metal structures, polymer structures, ceramics structures, glass structures, rubber structures, plastic structures, adhesive structures, micro-spring structures, microstructures of stress and impact buffer effect and a combination structure of the above structures.

11. A method of making a package structure as claimed in claim 1, wherein the formed interposers, micro-joints and microstructures for forming pre-bonding interface and connection between two substrates are prepared on one side of substrate and both sides of substrate;

wherein two of the substrates which are intended to be bonded together may have the said interposers, micro-joints and microstructures on one side of at least one of the substrates.

12. A method of making a package structure as claimed in claim 1, wherein the formed interposers, micro-joints and microstructures for forming pre-bonding interface and connection between two substrates are prepared on one side of substrate and both sides of substrate;

wherein two of the substrates which are intended to be bonded together may have the said interposers, micro-joints and microstructures on both sides of at least one of the substrates.

13. A method of making a package structure as claimed in claim 1, wherein the said interposers, micro-joints and microstructures are any shapes and morphology in three dimensional.

14. A method of making a package structure as claimed in claim 1, wherein the pre-bonding process are conducted with the aids of precision alignment tools;

wherein the pre-bonding process are conducted with the aids of additional energy coming from ultrasonic, heat, infrared radiation, or microwave source.

15. A method of making a package structure as claimed in claim 1, wherein the said interposers, micro-joints and microstructures structure for aligning and pre-bonding substrates can constitute an interface of enclosed-shape bonding ring, an interface of discrete bonding, contact area and the combination of these two formats on different locations of substrates.

16. A method of making a package structure as claimed in claim 1, wherein the materials used in the process of the said encapsulating interface process, in the other words, the said process of forming a completely sealed interface between the pre-bonded interfaces of substrates, are epoxy resin, polyimide, silicone, BCB (benzocy-clobutene), photo-resist, liquid crystal, polymers, rubbers, glasses, ceramics, metals and the combinations of these materials.

17. A method of making a package structure as claimed in claim 1, wherein a plural steps of the said aligning and pre-bonding process are done in order to make a bonded substrates which is a stack of multiple substrates.

18. A method of making a package structure as claimed in claim 1, wherein the materials used in the process of the said encapsulation process, in the other words, the said process of forming a completely sealed interface between the pre-bonded interfaces of substrates, are processes that liquid type encapsulating materials flows into the package structure through the through-hole microstructure when external extruding and pressing aids are used to accelerate the encapsulation process.

19. A method of making a package structure as claimed in claim 1, wherein the through-hole microstructures are made to be the inlet for encapsulating process.

20. A method of making a package structure as claimed in claim 1, wherein micro-channels and microstructures are made to lead the flow of encapsulating materials inside particular path and channel without overflowing to other area, then the said elements and three-dimensional structures are protected from damage during encapsulating process.

21. A method of making a package structure as claimed in claim 1, wherein the said package structure is provided with both fan-out and fan-in formats of electrical interconnections, electrical conductive lines, heat-transferring paths and heat dispatching paths;

the pitch between each pair of I/O are designed, changed and made according to different application needs;

the electrical signal are routed and arranged by making multilayer of electrical interconnections and insulating layers in order to make complex three-dimensional electrical interconnection structures thereof the said redistribution process.

22. A method of making a package structure as claimed in claim 1, wherein the electrical interconnection and signal I/O contacts inside the said package structure among different functional elements and dies are formed by bonding metal wires, depositing metal lines, plating metal lines, soldering, making conductive polymer and making bumping process of filp-chip technology.

23. A method of making a package structure as claimed in claim 1, wherein the optical interconnection and signal I/O contacts of the said package structure are formed by using optical waveguide elements, or adopting elements for enabling free space optical communications.

24. A method of making a package structure as claimed in claim 1, wherein the said package structure can consist of solder balls, solder bumps, solder lands and metal pads formed on the surface of one side and both sides of the said substrates.

25. A method of making a package structure as claimed in claim 1, wherein the signal I/O contacts of the said package structure to outside systems and other separate devices are metal pads for further wire bonding, UBM layers for further growing solder or gold bumps, a solder bumps, solder lands and metal pads for further surface mounting process.

26. A method of making a package structure as claimed in claim 1, wherein the said package structure, after pre-bonding and encapsulating steps, can have solder balls, solder bumps, solder lands and metal pads formed on the outside surface of one side and both sides of the said package structure.

27. A method of making a package structure as claimed in claim 1, wherein the said package structure can have heat-conductive pads to integrate or connect with heat-dispatching elements like fin, micro-fin, heat pipes, micro channels to enhance cooling performance.

28. A method of making a package structure as claimed in claim 1, wherein the said elements formed on substrate are made on a plurality of regions of substrate with spatial separation formed by lid or cover substrate for preventing the signal interference among the elements.

29. A method of making a package structure, comprising the steps of:

providing at least two substrates for composing the package structure;

making functional elements on at least one of the substrate;

fabricating alignment aiding microstructures

assembling discrete elements, dies and devices onto at least one of the substrate;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said substrates;

making electrical conduction line and lead line on at least one of the substrate for further constructing electrical conduction and signal connection between two different substrates;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the substrate

aligning and pre-bonding a substrate with the said alignment aiding microstructures, interposers and micro-joints to another substrate;

the process of alignment and bonding are done with the aids of alignment aiding microstructures which are formed on specific locations on upper side of a lower-substrate and on relative locations on backside of another upper-substrate, where the bonding interface is formed by connecting the aforementioned upper side to backside of two substrates;

thus a substrate of a stack of two substrates having a pre-bonded interface is formed;

forming a completely sealed interface between the pre-bonded interfaces of substrates by encapsulating the interfaces via through-hole microstructures, therefore a completely sealed package interface of each packaged devices or apparatus in the form of the said package is done and

separating each packaged structures, devices or apparatus in the form of the said package.

30. A method of making a package structure as claimed in claim 29, wherein the said substrates are materials of semiconductors, compound semiconductor, metals, plastics, polymers, ceramics and glasses.

31. A method of making a package structure as claimed in claim 29, wherein the said substrates are substrates of wafer form.

32. A method of making a package structure as claimed in claim 29, wherein the said function elements are microelectronics;

passive elements of resistors, capacitors and inductors;

optoelectronics;

laser diodes;

photo-detectors;

photo-sensors;

microelectromechanical systems, micro-fluidic systems, micro-total-analysis systems, bio-medical devices, bio-chips, bio-sensors and micro-opto-electro-mechanical systems.

33. A method of making a package structure as claimed in claim 29, wherein the said assembled and integrated functional elements, dies and devices inside the said package structure comprise plural functions, such as, computing, sensing, actuating, adjusting and controlling, then the said package structures are devices and apparatus in a format of system-in-a-package (SiP).

34. A method of making a package structure as claimed in claim 29, wherein the said assembled and integrated functional elements, dies and devices inside the said package structure comprise plural functions, such as, computing, sensing, actuating, adjusting and controlling;

wherein the said substrates are substrates of wafer form. Then the said package structures are devices and apparatus in a format of wafer-level-system-in-a-package (WLSiP).

35. A method of making a package structure as claimed in claim 29, wherein the technologies for assembling discrete elements or dies or devices onto at least one of the substrate are solder bonding, eutectic bonding, adhesive bonding, wire bonding and flip-chip bonding.

36. A method of making a package structure as claimed in claim 29, wherein the said interposers, micro-joints and microstructures between the pre-bonded substrates can make a spatial spacing of interface of appropriate height, therefore a space formed due to the microstructures of this height can offer a room to accommodate the protruding microstructures such as assembled elements, dies and devices;

three dimensional micro-electro-mechanical structures of sensors, actuators, three dimensional opto-electronics elements and fluidic channels.

37. A method of making a package structure as claimed in claim 29, wherein cavities made on the substrates before the pre-bonding process can lead to a spatial room of appropriate height inside the package structure after pre-bonding and encapsulating processes, therefore a space formed due to the cavities can offer a room to accommodate the protruding microstructures such as assembled elements, dies and devices;

three dimensional micro-electro-mechanical structures of sensors, actuators, three dimensional opto-electronics elements and fluidic channels, wherein the said cavities can have various heights.

38. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures, interposers and micro-joints are eutectic metal structures, solder structures, metal structures, polymer structures, ceramics structures, glass structures, rubber structures, plastic structures, adhesive structures, micro-spring structures, microstructures of stress and impact buffer effect and a combination structure of the above structures.

39. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures, interposers and micro-joints are any shapes and morphology in three dimensional.

40. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures, interposers and micro-joints, are three dimensional concave structures on one side of a substrate and be three dimensional convex structures on one side of another substrate, thereafter these said two sides will form the bonding interface.

41. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures can enhance the bonding interface strength;

wherein the said alignment aiding microstructures can enhance the mechanical strength of the contacting points for the electrical signal I/Os.

42. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures can have function of interface stress buffer and buffer for releasing the impact during pre-bonding and encapsulating process.

43. A method of making a package structure as claimed in claim 29, wherein the said alignment aiding microstructures are three dimensional micro-spring structures in order to have function of interface stress buffer and buffer for releasing the impact during pre-bonding and encapsulating process.

44. A method of making a package structure as claimed in claim 29, wherein the pre-bonding process are conducted with the aids of precision alignment tools;

wherein the pre-bonding process are conducted with the aids of additional energy coming from ultrasonic, heat, infrared radiation, or microwave source.

45. A method of making a package structure as claimed in claim 29, wherein the said interposers, micro-joints and microstructures structure for aligning and pre-bonding substrates can constitute an interface of enclosed-shape bonding ring, an interface of discrete bonding, contact area and the combination of these two formats on different locations of substrates.

46. A method of making a package structure as claimed in claim 29, wherein the materials used in the process of the said encapsulating interface process, in the other words, the said process of forming a completely sealed interface between the pre-bonded interfaces of substrates, are epoxy resin, polyimide, silicone, BCB (benzocy-clobutene), photo-resist, liquid crystal, polymers, rubbers, glasses, ceramics, metals and the combinations of these materials.

47. A method of making a package structure as claimed in claim 29, wherein the materials used in the process of the said encapsulating interface process, in the other words, the said process of forming a completely sealed interface between the pre-bonded interfaces of substrates, are processes that liquid type encapsulating materials flows into the package structure via the through-hole microstructures when external extruding and pressing aids are used to accelerate the encapsulation process.

48. A method of making a package structure as claimed in claim 29, wherein the through-hole microstructures are made to be the inlet for encapsulating process.

49. A method of making a package structure as claimed in claim 29, wherein micro-channels and microstructures are made to lead the flow of encapsulating materials inside particular path and channel without overflowing to other area, then the said elements and three dimensional structures are protected from damage during encapsulating process.

50. A method of making a package structure as claimed in claim 29, wherein plural steps of the said aligning and pre-bonding process are done in order to make bonded substrate, which is a stack of multiple substrates.

51. A method of making a package structure as claimed in claim 29, wherein the said package structure is provided with both fan-out and fan-in formats of electrical interconnections, electrical conductive lines, heat-transferring paths and heat dispatching paths;

the pitch between each pair of I/O are designed, changed and made according to different application needs;

the electrical signal are routed and arranged by making multilayer of electrical interconnections and insulating layers in order to complex three dimensional electrical interconnection structures thereof the said redistribution process.

52. A method of making a package structure as claimed in claim 29, wherein the electric interconnection and signal I/O contacts inside the said package structure among different functional elements and dies are formed by bonding metal wires, depositing metal lines, plating metal lines, soldering, making conductive polymer and making bumping process of flip-chip technology.

53. A method of making a package structure as claimed in claim 29, wherein the optical interconnection and signal I/O contacts of the said package structure are formed by using optical waveguide elements, or adopting elements for enabling free space optical communications.

54. A method of making a package structure as claimed in claim 29, wherein the said package structure can consist of solder balls, solder bumps, solder lands and metal pads formed on the surface of one side and both sides of the said substrates.

55. A method of making a package structure as claimed in claim 29, wherein the signal I/O contacts of the said package structure to outside systems and other separate devices are metal pads for further wire bonding, UBM layers for further growing solder, gold bumps and a solder bumps, solder lands and metal pads for further surface mounting process.

56. A method of making a package structure as claimed in claim 29, wherein the said package structure, after pre-bonding and encapsulating steps, can have solder balls, solder bumps, solder lands and metal pads formed on the outside surface of one side and both sides of the said package structure.

57. A method of making a package structure as claimed in claim 29, wherein the said package structure can have heat-conductive pads to integrate or connect with heat-dispatching elements like fin, micro-fin, heat pipes and micro channels to enhance cooling performance.

58. A method of making a package structure as claimed in claim 29, wherein the said elements formed on substrate are made on a plurality of regions of substrate with spatial separation formed by lid substrate for preventing the signal interference among the elements.

59. The method for making package structure,

providing at least two substrates for composing the package structure;

making functional elements on at least one of the substrate;

assembling discrete elements, dies and devices onto at least one of the substrate;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said substrates;

making electrical conduction line and lead line on at least one of the substrate for further constructing electrical conduction and signal connection between two different substrates;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the substrate;

aligning and pre-bonding a substrate with the said interposers, micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, may accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely sealed interface between the pre-bonded interfaces of substrates by applying fluidic encapsulating materials to seal the interfaces via through-hole microstructures, guiding the fluidic encapsulating materials inside the through-hole microstructures and package structures by making a difference of the internal and external pressure between the operating environment and the inner space of the said package structure;

Therefore, the flowability of the fluid encapsulating materials will become better, thus the space needed to be filled up are fulfilled perfectly and the encapsulating process will be finished faster;

therefore a completely sealed package interface of each packaged devices or apparatus in the form of the said package is done and

separating each packaged structures, devices or apparatus in the form of the said package.

60. The method for making package structure,

providing at least two substrates for composing the package structure;

making functional elements on at least one of the substrate;

assembling discrete elements, dies and devices onto at least one of the substrate;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said substrates;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the substrate;

forming getter coating and adding getter materials on substrates;

where the said getter are absorber and collector for various gases, liquids or solids;

aligning and pre-bonding a substrate with the said interposers micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, in order to accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely scaled interface between the pre-bonded interfaces of substrates by applying fluidic encapsulating materials to seal the interfaces via through-hole microstructures;

therefore a completely scaled package interface of each packaged devices or apparatus in the form of the said package is done and

separating each packaged structures, devices or apparatus in the form of the said package.

61. A method of making a package structure comprising:

providing at least two wafers for composing the package structure;

making functional elements on at least one of the wafer;

assembling discrete elements, dies and devices onto at least one of the wafer;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said wafers;

making electrical conduction line and lead line on at least one of the wafer for further constructing electrical conduction and signal connection between two different wafers;

executing the wafer level testing for measurement of system level performance of the said system-in-a-package (SiP) are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements;

during the wafer level testing process, the assembled elements and devices of malfunction are identified and replaced;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the wafer;

aligning and pre-bending a substrate with the said interposers, micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, in order to accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely sealed interface between the pre-bonded interfaces of substrates by encapsulating the interfaces via through-hole microstructures, therefore a completely sealed package interface of each packaged devices or apparatus in the form of the said package is done;

executing the wafer level testing to identify the good packaged structures and devices of the said system-in-a-package (SiP) format are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements and

separating each packaged structures, devices or apparatus in the form of the said package.

62. A method of making a package structure comprising:

providing at least two wafers for composing the package structure;

making functional elements on at least one of the wafer;

assembling discrete elements, dies and devices onto at least one of the wafer;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said wafers;

making electrical conduction line and lead line on at least one of the wafer for further constructing electrical conduction and signal connection between two different wafers;

executing the wafer level testing for measurement of system level performance of the said system-in-a-package (SiP) are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements;

during the wafer level testing process, the properties of the said passive elements and devices are trimmed to become better and precisely;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the wafer;

aligning and pre-bonding a substrate with the said interposes, micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, in order to accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely sealed interface between the pre-bonded interfaces of substrates by encapsulating the interfaces via through-hole microstructures, therefore a completely scaled package interlace of each packaged devices or apparatus in the form of the said package is done;

executing the wafer level testing to identify the good packaged structures and devices of the said system-in-a-package (SiP) format are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements and

separating each packaged structures, devices or apparatus in the form of the said package.

63. A method of making a package structure comprising:

providing at least two wafers for composing the package structure;

making functional elements on at least one of the wafer;

assembling discrete elements, dies and devices onto at least one of the wafer;

forming part of electrical interconnection among the integrated elements and assembled discrete elements on one side or both sides of the said wafers;

making electrical conduction line and lead line on at least one of the wafer for further constructing electrical conduction and signal connection between two different wafers;

executing the wafer level testing for measurement of system level performance of the said system-in-a-package (SiP) are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements;

forming interposers, micro-joints and microstructures on a portion of surface of at least one of the wafer;

aligning and pre-bonding a substrate with the said interposers, micro-joints and microstructures to another substrate;

thereafter, the appropriate spacing provided by the corresponding said interposers, micro-joints and microstructures between the pre-bonded substrates, in order to accommodate and protect the integrated and hybrid assembled elements on the substrates;

forming a completely scaled interface between the pre-bonded interfaces of substrates by encapsulating the interfaces via through-hole microstructures, therefore a completely sealed package interface of each packaged devices or apparatus in the form of the said package is done;

executing the wafer level testing to identify the good packaged structures and devices of the said system-in-a-package (SiP) format are proceeded by using probes and probe card to contact the metal pads and conductive microstructures of the said package structures to form the electrical connection between the testing equipment and elements needed to be tested;

then signals and bias are applied to measure and test the said elements;

the said package structure are put into the environmental testing oven, and with the probes or wafer-level probe card for applying external signals and bias, in order to proceed the reliability testing, such as, aging treatment tests, and the burn-in process and

separating each packaged structures, devices or apparatus in the form of the said package.