Flash memory device and a method for fabricating the same

• US 6,784,055 B2
• Filed: 04/18/2003
• Issued: 08/31/2004
• Est. Priority Date: 03/17/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jong-Woo, Choi, Jung-Dal, Shin, You-Cheol
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US10/418,701
• Publication Number:
  US 20030205727A1
• Time in Patent Office: 501 Days
• Field of Search: 438/257, 438/262, 438/427, 438/431, 257/314-323, 257/298
• US Class Current: 438/257
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

Claims

1. A method for forming a flash memory device, comprising:

sequentially forming a charge-storage dielectric layer and an etching mask layer on a semiconductor substrate;

patterning the etching mask layer and the charge-storage layer, thereby exposing regions of the semiconductor substrate;

forming isolation regions in the exposed regions of the semiconductor substrate, the isolation regions defining active regions;

removing the patterned etching mask layer;

forming an upper conductive layer overlying the patterned charge-storage layer; and

patterning the upper conductive layer and the patterned charge-storage layer, thereby forming a gate line intersecting the isolation regions and the active regions.

2. The method of claim 1, wherein the charge-storage layer includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially stacked on the semiconductor substrate.

3. The method of claim 1, further comprising forming a lower conductive layer between the charge-storage layer and the etching mask layer,

wherein the lower conductive layer is patterned when the etching mask layer and the charge-storage layer are patterned; and

wherein the patterned lower conductive layer is patterned when the upper conductive layer and the patterned charge-storage layer are patterned.

4. The method of claim 1, wherein forming the isolation regions in the exposed regions of the semiconductor substrate further comprises:

etching the exposed regions of the semiconductor substrate to form trenches therein; and

filling the trenches with a trench-filling insulating layer.

5. The method of claim 4, further comprising:

planarizing the trench-filling insulating layer until a top surface of the patterned etching mask layer is exposed.

6. The method of claim 5, wherein the charge-storage layer includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially stacked on the semiconductor substrate.

7. The method of claim 1, wherein forming the isolation regions on the exposed regions of the semiconductor substrate further includes:

forming a thermal oxide layer on the exposed semiconductor substrate.

8. The method of claim 7, wherein the charge-storage layer includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially stacked on the semiconductor substrate.

9. A method for forming a flash memory comprising:

sequentially forming a charge-storage dielectric layer, a lower conductive layer, and an etching mask layer on a semiconductor substrate;

patterning the etching mask layer, the lower conductive layer, and the charge-storage dielectric layer, thereby exposing regions of the semiconductor substrate;

etching the exposed regions of the semiconductor substrate to form trenches therein;

filling the trenches with a trench-filling insulating layer;

planarizing the trench-filling insulating layer until the patterned etching mask layer is exposed, thereby forming isolation regions defining active regions therebetween;

removing the exposed patterned etching mask layer;

forming an upper conductive layer on the isolation regions and the patterned lower conductive layer; and

patterning the upper conductive layer, the patterned lower conductive layer, and the patterned charge-storage layer, thereby forming gate lines intersecting the isolation regions and active regions.

10. The method of claim 9, wherein the charge-storage layer includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially stacked on the semiconductor substrate.

11. A method for forming flash memory device comprising:

forming a charge-storage layer on a semiconductor substrate;

patterning the charge-storage layer to expose regions of the semiconductor substrate,

forming isolation regions in the exposed regions of the semiconductor substrate, the isolation regions defining active regions therebetween, the patterned charge-storage layer self-aligned with the isolation regions;

forming a conductive layer overlying the patterned charge-storage layer; and

patterning the conductive layer and the patterned charge-storage layer to form gate lines overlying the patterned charge-storage layer, the gale lines extending across the active regions.

12. The method of claim 11, wherein the charge-storage layer includes a lower oxide layer, a nitride layer, and an upper oxide layer (ONO layer) sequentially stacked on the semiconductor substrate.

13. A method for fanning a flash memory device, comprising:

sequentially forming a lower oxide layer, a nitride layer, an upper oxide layer (ONO layer) as a charge-storage layer and an etching mask layer an a semiconductor substrate;

patterning the etching mask layer and the ONO layer, thereby exposing regions of the semiconductor substrate;

etching the exposed regions of the semiconductor substrate to form trenches therein, and filling the trenches with a trench-filling insulating layer to form trench isolation regions defining active regions;

removing the patterned etching musk layer; and

forming an upper conductive layer and the patterned ONO layer, thereby forming a gate line intersecting the trench isolation regions and the active regions.

14. The method of claim 13, further comprising forming a lower conductive layer between the ONO layer and the etching mask layer, wherein the lower conductive layer is patterned when the etching mask layer and the ONO layer are patterned, and wherein the patterned lower conductive layer is patterned when an upper conductive layer patterned and the ONO layer are patterned.

15. The method of claim 13, further comprising:

planarizing the trench-filling insulating layer until a top surface of the patterned etching mask layer is exposed.

16. The method of claim 13, further comprising:

forming a thermal oxide layer overlying the trenches.

17. The method of claim 13, further comprising:

sequentially forming a thermal oxide and a nitride liner overlying the trenches.