Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation

• US 6,784,101 B1
• Filed: 05/16/2002
• Issued: 08/31/2004
• Est. Priority Date: 05/16/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin, Wu, David
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US10/146,029
• Time in Patent Office: 838 Days
• Field of Search: 438/666, 438/197-201, 438/287, 438/585-596, 438/216, 438/261, 438/785, 257/288, 257/285-296, 257/368-369, 257/410-413, 257/900
• US Class Current: 438/666
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.

Claims

1. A method of manufacturing a semiconductor device, comprising sequential steps of:

(a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof, said strained lattice semiconductor layer having a pre-sleeted amount of lattice strain therein;

(b) forming a thin buffer/interfacial layer of a low-k dielectric material on said upper surface of said semiconductor substrate; and

(c) forming a layer of a high-k dielectric material on said thin buffer/interfacial layer of a low-k dielectric material, wherein;

steps (b) and (c) are each performed at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.

2. The method as in claim 1, wherein:

step (a) comprises providing a semiconductor substrate including a crystalline, graded composition Si—

Ge layer, with a lattice-matched crystalline silicon (Si) layer on a first side of said Si—

Ge layer and comprising said strained lattice semiconductor layer.

3. The method as in claim 2, wherein:

step (a) further comprises providing a semiconductor substrate including a crystalline Si layer on a second, opposite side of said Si—

Ge layer.

4. The method as in claim 1, wherein:

step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material having a dielectric constant k less than 5.

5. The method as in claim 4, wherein:

step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material at a thickness from about 2 to about 6 Å

.

6. The method as in claim 4, wherein:

step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material from at least one material selected from the group consisting of silicon oxides and silicon oxynitrides.

7. The method as in claim 5, wherein:

step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material at a temperature ranging from about 200 to about 400°

C.

8. The method as in claim 7, wherein:

step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material by an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam deposition (MBD), and physical vapor deposition (PVD).

9. The method as in claim 1, wherein:

step (c) comprises forming said layer of a high-k dielectric material having a dielectric constant k greater than 5.

10. The method as in claim 9, wherein:

step (c) comprises forming said layer of a high-k dielectric material at a thickness from about 40 to about 100 Å

.

11. The method as in claim 9, wherein:

step (c) comprises forming said layer of a high-k dielectric material from at least one metal and oxygen-containing material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and tenary metal oxides.

12. The method as in claim 11, wherein:

step (c) comprises forming said layer of a high-k dielectric material from at least one material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, yttrium oxide, zirconium silicate, hafnium silicate, hafnium aluminae, lathanum aluminate, lead titanate, barium titanate, strontium titanate, barium strontium titante, lead zirconate;

ferroelectric oxides, ternary metal oxides, PST (PbSc_xTa<sub>1−

x</sub>O₃), PZN (PbZn_xNb<sub>1−

x</sub>O₃), PZT (PbZ_rTi<sub>1−

x</sub>O₃), and PMN (PbMg_xNb<sub>1−

x</sub>O₃).

13. The method as in claim 9, wherein:

step (c) comprises forming said layer of a high-k dielectric material at a temperature ranging from about 200 to about 400°

C.

14. The method as in claim 13, wherein:

step (c) comprises forming said layer of a high-k dielectric material by an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam disposition (MBD), and physical vapor deposition (PVD).

15. The method as in claim 1, further comprising sequential steps of:

(d) forming an electrically conductive layer on said layer of a high-k dielectric material; and

(e) patterning said electrically conductive layer, said layer of a high-k dielectric material, and said thin buffer layer of a low-k dielectric material to form at least one gate insulator layer/gate electrode stack on at least one portion of said upper surface of said semiconductor substrate.

16. The method as in claim 15, further comprising the step of:

(f) implanting dopant species of one conductivity type into said semiconductor substrate utilizing said at least one gate insulator layer/gate electrode stack as an implantation mask, thereby forming at least one pair of shallow depth source/drain extension regions in said semiconductor substrate vertically aligned with opposite side edges of said at least one gate insulator layer/gate electrode stack.

17. The method as in claim 16, further comprising sequential steps of:

(g) forming insulative sidewall spacers on said opposite side edges of said at least one gate insulator layer/gate electrode stack;

(h) implanting dopant species of said one conductivity type into said semiconductor substrate utilizing said at least one gate insulator layer/gate electrode stack with said insulative sidewall spacers thereon as an implantation mask, thereby forming at least one pair of deeper source/drain regions in said semiconductor substrate vertically aligned with opposite side edges of said sidewall spacers; and

(i) thermally annealing the thus-formed structure for a minimum interval sufficient to activate said dopant species implanted in said at least one pair of shallow depth source/drain regions and in said at least one pair of deeper source/drain regions without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.

18. The method as in claim 17, wherein:

step (i) comprises performing laser thermal annealing (LTA) or rapid thermal annealing (RTA) at a temperature from about 1,200 to about 1,400°

C. for from about 1 to about 100 nanosec.

19. A PMOS or NMOS transistor manufactured according to the method of claim 18.

20. A CMOS or IC device manufactured according to the method of claim 18.