Vertical power devices having retrograded-doped transition regions therein

• US 6,784,486 B2
• Filed: 07/19/2002
• Issued: 08/31/2004
• Est. Priority Date: 06/23/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US10/199,583
• Publication Number:
  US 20020185679A1
• Time in Patent Office: 774 Days
• Field of Search: 257/327-329, 257/341-345, 257/491-493, 257/496
• US Class Current: 257/327
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Power MOSFET devices provide highly linear transfer characteristics (e.g., I_d v. V_g) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Claims

1. A vertical power device, comprising:

a semiconductor substrate;

a drift region of first conductivity type in said semiconductor substrate;

first and second spaced-apart base regions of second conductivity type in said semiconductor substrate;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to a surface of said semiconductor substrate; and

an insulated gate electrode that extends on the surface and opposite said first base region and said transition region.

2. The device of claim 1, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

3. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

4. The device of claim 3, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

5. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm².

6. The power device of claim 5, wherein said insulated gate electrode, said first source region, said first base region, said transition region and said drift region collectively define an insulated-gate field effect transistor that is configured to support an inversion-layer channel in said first base region during forward on-state conduction, said inversion-layer channel being operable in a linear mode of operation while the drift region simultaneously operates in a velocity saturation mode of operation.

7. The device of claim 5, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

8. The device of claim 1, further comprising:

a first shielding region of second conductivity type that extends between said first base region and the drift region and is more highly doped than said first base region; and

a second shielding region of second conductivity type that extends between said second base region and the drift region and is more highly doped than said second base region.

9. The device of claim 8, wherein said first and second shielding regions form respective P-N rectifying junctions with said transition region;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width between said first and second shielding regions is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

10. The device of claim 9, wherein the peak first conductivity type dopant concentration in said transition region is greater than about 1×

10¹⁷ cm<sup>−

3</sup>;

wherein the surface defines an interface between said insulated gate electrode and said transition region; and

wherein a first conductivity type dopant concentration in said transition region is less than about 2×

10¹⁶ cm^{F31 3} at the surface.

11. The power device of claim 1, wherein said insulated gate electrode, said first source region, said first base region, said transition region and said drift region collectively define an insulated-gate field effect transistor that is configured to support an inversion-layer channel in said first base region during forward on-state conduction, said inversion-layer channel being operable in a linear mode of operation while the drift region simultaneously operates in a velocity saturation mode of operation.