Low capacitance ESD protection device and integrated circuit including the same

• US 6,784,498 B1
• Filed: 03/31/2003
• Issued: 08/31/2004
• Est. Priority Date: 11/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Wu, Yi-Hsun
• Primary Examiner(s): Chen, Jack
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/403,976
• Time in Patent Office: 519 Days
• Field of Search: 257/355, 257/357, 257/360, 257/361
• US Class Current: 257/361
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.

Claims

1. A low capacitance ESD protection device comprising:

a substrate;

a well of a first conductivity type in the substrate;

a first and second transistor of the first conductivity type respectively on two sides of the well;

a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor; and

a doped region of the second conductivity type in the well;

wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

2. The ESD protection device as claimed in claim 1 further comprising a second guard ring of the first conductivity type in the substrate, surrounding the guard ring of the second conductivity type.

3. The ESD protection device as claimed in claim 2, wherein the second guard ring is coupled to receive a first voltage level.

4. The ESD protection device as claimed in claim 3, wherein the first voltage level is a power supply voltage Vcc.

5. The ESD protection device as claimed in claim 1 further comprising a conducting layer on the doped region, having a first, second and third portion separated from each other by gaps, and respectively coupled to a pad, the drain region of the first transistor and the drain region of the second transistor.

6. The ESD protection device as claimed in claim 5, wherein the conducting layer is a silicide layer.

7. The ESD protection device as claimed in claim 1, wherein the doped region, and the drain regions of the first and second transistor are coupled to a pad, and the guard ring, and the source regions of the first and second transistor are coupled to receive a second voltage level.

8. The ESD protection device as claimed in claim 7, wherein the second voltage level is a power supply voltage Vss.

9. The ESD protection device as claimed in claim 1, wherein the first and second conductivity type are N and P type respectively.

10. A low capacitance ESD protection device comprising:

a substrate;

a well of a first conductivity type in the substrate;

a first and second transistor of the first conductivity type respectively on two sides of the well;

a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor; and

a doped region of the second conductivity type in the well;

wherein, for each of the first and second transistor, a width of a drain region is substantially equal to that of a source region and a length of the drain region is shorter than that of the source region.

11. The ESD protection device as claimed in claim 10 further comprising a second guard ring of the first conductivity type in the substrate, surrounding the guard ring of the second conductivity type.

12. The ESD protection device as claimed in claim 11, wherein the second guard ring is coupled to receive a first voltage level.

13. The ESD protection device as claimed in claim 12, wherein the first voltage level is a power supply voltage Vcc.

14. The ESD protection device as claimed in claim 10 further comprising a conducting layer on the doped region, having a first, second and third portion separated from each other by gaps, and respectively coupled to a pad, the drain region of the first transistor and the drain region of the second transistor.

15. The ESD protection device as claimed in claim 14, wherein the conducting layer is a silicide layer.

16. The ESD protection device as claimed in claim 10, wherein the doped region, and the drain regions of the first and second transistor are coupled to a pad, and the guard ring, and the source regions of the first and second transistor are coupled to receive a second voltage level.

17. The ESD protection device as claimed in claim 16, wherein the second voltage level is a power supply voltage Vss.

18. The ESD protection device as claimed in claim 10, wherein the first and second conductivity type are N and P type respectively.

19. An integrated circuit comprising:

a core circuit; and

a low capacitance ESD protection device protecting the core circuit form ESD damages, comprising;

a substrate;

a well of a first conductivity type in the substrate;

a first and second transistor of the first conductivity type respectively on two sides of the well;

a guard ring of a second conductivity type in the substrate, surrounding the well; and

the first and second transistor; and

a doped region of the second conductivity type in the well,

wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

20. The integrated circuit as claimed in claim 19, wherein the low capacitance ESD protection device further comprises a second guard ring of the first conductivity type in the substrate, surrounding the guard ring of the second conductivity type.

21. The integrated circuit as claimed in claim 20, wherein the second guard ring is coupled to receive a first voltage level.

22. The integrated circuit as claimed in claim 21, wherein the first voltage level is a power supply voltage Vcc.

23. The integrated circuit as claimed in claim 19, wherein the low capacitance ESD protection device further comprises a conducting layer on the doped region, having a first, second and third portion separated from each other by gasps, and respectively coupled to a pad, the drain region of the first transistor and the drain region of the second transistor.

24. The integrated circuit as claimed in claim 23, wherein the conducting layer is a silicide layer.

25. The integrated circuit as claimed in claim 19, wherein the doped region, and the drain regions of the first and second transistor are coupled to a pad, and the guard ring, and the source regions of the first and second transistor are coupled to receive a second voltage level.

26. The integrated circuit as claimed in claim 25, wherein the second voltage level is a power supply voltage Vss.

27. The integrated circuit as claimed in claim 19, wherein the first and second conductivity type are N and P type respectively.