Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique

• US 6,784,505 B2
• Filed: 05/03/2002
• Issued: 08/31/2004
• Est. Priority Date: 05/03/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US10/138,913
• Publication Number:
  US 20030205758A1
• Time in Patent Office: 851 Days
• Field of Search: 257/341, 257/287, 257/493, 257/401, 257/397, 257/E21.546, 257/E21.572, 257/E21.549, 257/E29.201, 257/E29.257, 257/E21.551, 257/E27.091, 257/E29.26, 438/589
• US Class Current: 257/397
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N⁺ substrate can be terminated at the edge of the die.

Claims

1. A power mosfet with trench gates comprising:

a semiconductor substrate;

a drain layer on one surface of the substrate doped with a high concentration of a dopant of one polarity;

an epitaxial layer above the drain layer and lightly doped with a dopant of opposite polarity;

a source layer at the other surface of the substrate and doped with a high concentration of the same dopant as the drain layer;

a plurality of trenches penetrating the source layer, said trenches substantially filled with conductive gate polycrystalline material doped with the same dopant type as the source layer; and

a drift layer in the substrate forming a continuous lightly doped drift region extending between sidewalls of the trenches and from the drain layer toward the source region and along a lower portion of the trench sidewalls to provide a variable, lightly doped concentration that gradually decreases in density from the sidewalls of the trenches toward a plane about midway between the trenches.

2. A power mosfet with trench gates comprising:

a semiconductor substrate;

a drain layer on one surface of the substrate doped with a high concentration of a dopant of one polarity;

an epitaxial layer above the drain layer and lightly doped with a dopant of opposite polarity;

a source layer at the other surface of the substrate and doped with a high concentration of the same dopant as the drain layer;

a plurality of trenches penetrating the source layer, said trenches substantially filled with conductive gate polycrystalline material doped with the same dopant type as the source layer; and

a drift layer in the substrate forming a continuous lightly doped drift region extending between sidewalls of the trenches and from the drain layer toward the source region and along a lower portion of the trench sidewalls to provide a variable, lightly doped concentration that gradually decreases in density from the sidewalls of the trenches toward a plane about midway between the trenches;

a BPSG layer over the gate material in the trenches; and

an edge termination having a vertical face comprising a layer of field oxide, a layer of polysilicon, and a layer of BPSG over the epitaxial region and a recessed outer horizontal face, a heavily doped region on outer edge of the die to form a channel stop region in the epitaxial layer and a channel stopper metal layer over and in contact with the channel stop region.

3. A power mosfet with trench gates comprising:

a semiconductor substrate having a drain layer heavily doped with dopants of one polarity;

an epitaxial layer on the substrate and comprising dopants of an opposite polarity;

a plurality of source regions on the surface of the epitaxial layer and heavily doped with dopants of the same polarity as the drain;

a plurality of trenches penetrating the source regions, separated from the epitaxial layer by a gate insulating layer and comprising conductive material;

channel regions in the epitaxial layer adjacent the gate insulating layer of the trenches; and

a continuous drift layer comprising dopants of the same polarity as the source and drain and disposed in the epitaxial layer adjacent the substrate and extending toward the floors of the trenches and between the trenches, said continuous drift layer having a variable and lightly doped concentration of dopants between the trenches with a maximum concentration at the trench sidewall and gradually decreasing in concentration toward a plane midway between the trenches.

4. The power mosfet of claim 3 wherein the dopant concentration in the channel regions are substantially flat across most of the channel.