Closed-grid bus architecture for wafer interconnect structure

• US 6,784,677 B2
• Filed: 04/02/2003
• Issued: 08/31/2004
• Est. Priority Date: 07/10/2000
• Status: Expired due to Term

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Long, John Matthew, Miller, Charles A.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US10/406,669
• Publication Number:
  US 20030169061A1
• Time in Patent Office: 517 Days
• Field of Search: 324/754, 324/757, 324/758, 324/761, 324/765, 324/158.1, 298/25, 298/29
• US Class Current: 324/750.3
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/0289 having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
• CPC Class Codes: H05K 2201/09254 Branched layout
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Claims

1. An apparatus for distributing a signal from a signal source to a plurality of destination nodes, the apparatus comprising:

an array of bus nodes having at least three rows and three columns of bus nodes, each bus node corresponding to a separate one of said plurality of destination nodes, each row of bus nodes including at least three bus nodes, and each column of said bus nodes including at least three bus nodes;

a plurality of first daisy-chain buses, one for each of said rows of bus nodes, each first daisy-chain bus linking all bus nodes of a separate one of said rows of bus nodes, and each first daisy-chain bus having two ends;

at least one second daisy-chain bus, each corresponding to a separate one of said columns of bus nodes and linking all bus nodes of the corresponding one of said columns of bus nodes;

a plurality of conductors, each connected near said ends of said first daisy-chain buses, such that each first daisy-chain bus is linked to at least one other of said first daisy-chain buses, and such that said conductors and said first and second daisy-chain buses form a closed-grid bus conductively interconnecting all of said bus nodes of said array of bus nodes;

first means for conductively linking said closed-grid bus to said signal source; and

second means for conductively linking each of said bus nodes to its corresponding destination node.

2. The apparatus in accordance with claim 1 wherein said second means comprises:

a plurality of isolation resistors, each isolation resistor being connected to a corresponding bus node of said array of bus nodes; and

third means for linking each of said isolation resistors to a separate one of said destination nodes.

3. The apparatus in accordance with claim 1 further comprising:

a first circuit board layer; and

a second circuit board layer,

wherein said plurality of first daisy-chain buses comprise first traces formed on said first circuit board layer,

wherein said plurality of second daisy-chain buses and said plurality of conductors comprise second traces formed on said second circuit board layer, and

wherein said array of bus nodes comprises an array of first vias extending through one of said first and second circuit board layers.

4. The apparatus in accordance with claim 3 wherein said second means comprises:

a plurality of isolation resistors, each isolation resistor being connected to a corresponding bus node of said array of bus nodes; and

third means for linking each of said isolation resistors to a separate one of said destination nodes.

5. The apparatus in accordance with claim 4 further comprising:

a third circuit board layer, wherein said plurality of isolation resistors are mounted on said third circuit board layer; and

a plurality of second vias extending through at least one of said first, second and third layers and linking each isolation resistor to its corresponding bus node.

6. An apparatus for providing a signal path between an integrated circuit tester channel and an array of input/output (I/O) pads on a semiconductor wafer, the apparatus comprising:

a circuit board including a first circuit board layer and a second circuit board layer;

an array of vias extending through at least one of said first and second circuit board layers having at least three rows and three columns of vias, each via corresponding to a separate one of said I/O pads, each row of vias including at least three vias, and each column of vias including at least three vias;

first traces mounted on said first circuit board layer and extending in a first direction, one for each row of said vias, each first trace linking all vias of its corresponding row of vias;

second traces mounted on said second circuit board layer and extending in a second direction, each second trace corresponding to a separate column of said vias and linking all vias of its corresponding column of vias, wherein said first and second traces and said vias form a closed-grid bus;

first means for conductively linking said closed-grid bus to said tester channel; and

second means for conductively linking each of said vias to its corresponding I/O pad.

7. The apparatus in accordance with claim 6 wherein said second means comprises:

a plurality of isolation resistors, each isolation resistor being conductively linked to a corresponding via of said array of vias; and

third means for conductively linking each isolation resistor to a separate one of said I/O pads.

8. The apparatus in accordance with claim 7 further comprising:

a third circuit board layer, said plurality of isolation resistors being mounted on said third circuit board layer; and

fourth means for conductively linking each isolation resistor to its corresponding via.

9. The apparatus in accordance with claim 8 wherein said third means comprises additional vias extending through at least one of said first, second and third circuit board layers.

10. The apparatus in accordance with claim 6 wherein said second means for conductively linking each of said vias to its corresponding I/O pad comprises:

a plurality of contact pads mounted on said circuit board, each corresponding to a separate one of said I/O pads;

means for conductively linking each contact pad to a separate one of said vias; and

a plurality of spring contacts, each extending between a separate one of said no pads and its corresponding contact pad.

22. The apparatus in accordance with claim 6 wherein the second direction is orthogonal to the first direction.

11. A method for distributing a signal from a signal source to a plurality of destination nodes, the method comprising the steps of:

a. providing an array of bus nodes having at least three rows and three columns of bus nodes, each bus node corresponding to a separate one of said plurality of destination nodes, each row of bus nodes including at least three bus nodes, and each column of said bus nodes including at least three bus nodes;

b. providing a plurality of first daisy-chain buses, one for each of said rows of bus nodes, each first daisy-chain bus linking all bus nodes of a separate one of said rows of bus nodes, and each first daisy-chain bus having two ends;

c. providing at least one second daisy-chain bus, each corresponding to a separate one of said columns of bus nodes and linking all bus nodes of the corresponding one of said columns of bus nodes;

d. providing a plurality of conductors, each connected near said ends of said first daisy-chain buses, such that each first daisy-chain bus is linked to at least one other of said first daisy-chain buses, and such that said conductors and said first and second daisy-chain buses form a closed-grid bus conductively interconnecting all of said bus nodes of said array of bus nodes;

e. conductively linking said closed-grid bus to said signal source; and

f. conductively linking each of said bus nodes to its corresponding destination node.

12. The method in accordance with claim 11 wherein step f comprises connecting a separate isolation resistor between each bus node of said array of bus nodes and that bus node'"'"'s corresponding destination node.

13. The method in accordance with claim 11

wherein said plurality of first daisy-chain buses comprise first traces formed on a first layer of a circuit board,

wherein said plurality of second daisy-chain buses and said plurality of conductors comprise second traces formed on a second layer of the circuit board, and

wherein said array of bus nodes comprises an array of first vias extending through one of said first and second circuit board layers.

14. The method in accordance with claim 13 wherein step f comprises connecting a separate isolation resistor between each bus node of said array of bus nodes and that bus node'"'"'s corresponding destination node.

15. The method in accordance with claim 14

wherein each isolation resistor is mounted on a third layer of the circuit board, and

wherein step f further comprises the step of providing a plurality of second vias extending

 

through at least one of said first, second and third layers and linking each isolation resistor to its corresponding bus node.

16. A method for providing a signal path between an integrated circuit tester channel and an array of input/output (I/O) pads on a semiconductor wafer, the method comprising the steps of:

a. providing a circuit board including a first substrate layer and a second substrate layer;

b. forming an array of vias extending through at least one of said first and second substrate layers having at least three rows and three columns of vias, each via corresponding to a separate one of said I/O pads, each row of vias including at

 

least three vias, and each column of vias including at least three vias;

c. forming first traces on said first substrate layer extending in a first direction, one for each row of said vias, each first trace linking all vias of its corresponding row of vias;

d. forming second traces on said second substrate layer extending in a second direction, each second trace corresponding to a separate column of said vias and linking all vias of its corresponding column of vias, wherein said first and second traces and said vias form a closed-grid bus;

e. conductively linking said closed-grid bus to said tester channel; and

f. conductively linking each of said vias to its corresponding I/O pad.

17. The method in accordance with claim 16 wherein step f comprises the substeps of:

f1. connecting a separate isolation resistor to each via of the array of vias; and

f2. conductively linking each isolation resistor to a separate one of said I/O pads.

18. The method in accordance with claim 17 wherein each isolation resistor is mounted on a third substrate layer of the circuit board.

19. The method in accordance with claim 17 wherein each isolation resistor is linked to a separate one of said I/O pads through a including path including an additional via extending through at least one of said first, second and third circuit board layers.

20. The method in accordance with claim 17 wherein step f2 comprises the substeps of:

f21. mounting a plurality of contact pads on said circuit board, each corresponding to a separate one of said I/O pads;

f22. conductively linking each contact pad to a separate one of said isolation resistors; and

f23. providing a plurality of spring contacts, each extending between a separate one of said I/O pads and its corresponding contact pad.

21. The method in accordance with claim 16 wherein the second direction is orthogonal to the first direction.