Sense amplifier with improved common mode rejection

• US 6,784,698 B1
• Filed: 06/11/2003
• Issued: 08/31/2004
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Brenden, Jason P.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/459,058
• Time in Patent Office: 447 Days
• Field of Search: 327/51, 327/52, 327/54, 327/560-563, 327/536, 323/311-316, 323/364, 318/432-434, 318/825, 330/252-260
• US Class Current: 327/51
• CPC Class Codes: H03F 2203/45352 the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
• CPC Class Codes: H03F 2203/45392 the AAC comprising resistors in the source circuit of the AAC before the common source coupling
• CPC Class Codes: H03F 2203/45574 the IC comprising four or more input leads connected to four or more AAC-transistors
• CPC Class Codes: H03F 3/3062 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45654 Controlling the active amplifying circuit of the differential amplifier

Abstract

A sense amplifier having improved common mode rejection has a differential input and a differential output. A first level shifting transconductance circuit is connected to receive the differential input. A gain and compensation circuit is connected to the level shifting transconductance circuit, and a buffer is connected to the gain and compensation circuit. The differential output of the sense amplifier is taken at an output of the buffer. A feedback network is connected between the output of the buffer and an input of the gain and compensation circuit. The feedback network includes a divider circuit connected to the output of the buffer and a second level shifting transconductance circuit connected between the divider circuit and the input of the gain and compensation circuit. The first and second level shifting transconductance circuits are preferably matched to one another for distortion cancellation.

Claims

1. A sense amplifier having a differential input and a differential output, the sense amplifier comprising:

a first level shifting transconductance circuit connected to receive the differential input;

a gain and compensation circuit connected to the level shifting transconductance circuit;

a buffer connected to the gain and compensation circuit, wherein the differential output of the sense amplifier is taken at an output of the buffer; and

a first feedback network connected between the output of the buffer and an input of the gain and compensation circuit, comprising;

a divider circuit connected to the output of the buffer; and

a second level shifting transconductance circuit connected between the divider circuit and the input of the gain and compensation circuit.

2. The sense amplifier of claim 1, wherein the first and second level shifting transconductance circuits are identically matched to one another.

3. The sense amplifier of claim 1, further comprising a second feedback network connected between the output of the buffer and the gain and compensation circuit to set a common mode output of the sense amplifier.

4. The sense amplifier of claim 1, wherein the first and second level shifting transconductance circuits each comprise:

a first pair of transistors comprising;

a first transistor connected to a first node of the differential input; and

a second transistor connected to a second node of the differential input;

a second pair of transistors comprising;

a third transistor connected to the first node of the differential input; and

a fourth transistor connected to the second node of the differential input;

a third pair of transistors comprising;

a fifth transistor having a control region connected to the first transistor and having a first controlled region connected to the third transistor in a cascode configuration; and

a sixth transistor having a control region connected to the second transistor and having a first controlled region connected to the fourth transistor in a cascode configuration;

a first degeneration resistor connected to a second controlled region of the fifth transistor; and

a second degeneration resistor connected to a second controlled region of the sixth transistor.

5. The sense amplifier of claim 4, wherein bulk connections of the first, second, third, fourth, fifth and sixth transistors are connected to a common voltage.

6. The sense amplifier of claim 4, wherein the first, second, third and fourth transistors are high voltage MOS devices, and the fifth and sixth transistors are low voltage MOS devices.

7. The sense amplifier of claim 1, wherein the divider circuit is a divide-by-three circuit.

8. The sense amplifier of claim 1, wherein the divider circuit is a resistive circuit.

9. The sense amplifier of claim 1, having all components realized in an integrated circuit (IC).

10. A feedback control system for driving a load in response to a differential input command signal, comprising:

an error amplifier and compensation circuit receiving the differential input command signal;

a power amplifier connected to an output of the error amplifier and compensation circuit;

a sense resistor connected between an output of the power amplifier and the load; and

a sense amplifier having an input connected across the sense resistor to detect a current flowing through the sense resistor, and having an output connected to an input of the error amplifier and compensation circuit, the sense amplifier comprising;

a first level shifting transconductance circuit connected to receive the differential input;

a gain and compensation circuit connected to the level shifting transconductance circuit;

a buffer connected to the gain and compensation circuit, wherein the differential output of the sense amplifier is taken at an output of the buffer; and

a first feedback network connected between the output of the buffer and an input of the gain and compensation circuit, comprising;

a divider circuit connected to the output of the buffer; and

a second level shifting transconductance circuit connected between the divider circuit and the input of the gain and compensation circuit.

11. The feedback control system of claim 10, wherein the first and second level shifting transconductance circuits of the sense amplifier are identically matched to one another.

12. The sense amplifier of claim 10, wherein the sense amplifier further comprises a second feedback network connected between the output of the buffer and the gain and compensation circuit to set a common mode output of the sense amplifier.

13. The sense amplifier of claim 10, wherein the first and second level shifting transconductance circuits of the sense amplifier each comprise:

a first pair of transistors comprising;

a first transistor connected to a first node of the differential input; and

a second transistor connected to a second node of the differential input;

a second pair of transistors comprising;

a third transistor connected to the first node of the differential input; and

a fourth transistor connected to the second node of the differential input;

a third pair of transistors comprising;

a fifth transistor having a control region connected to the first transistor and having a first controlled region connected to the third transistor in a cascode configuration; and

a sixth transistor having a control region connected to the second transistor and having a first controlled region connected to the fourth transistor in a cascode configuration;

a first degeneration resistor connected to a second controlled region of the fifth transistor; and

a second degeneration resistor connected to a second controlled region of the sixth transistor.

14. The feedback control circuit of claim 13, wherein bulk connections of the first, second, third, fourth, fifth and sixth transistors of the first and second level shifting transconductance circuits of the sense amplifier are connected to a common voltage.

15. The feedback control circuit of claim 13, wherein the first, second, third and fourth transistors of the first and second level shifting transconductance circuits of the sense amplifier are high voltage MOS devices, and the fifth and sixth transistors of the first and second level shifting transconductance circuits of the sense amplifier are low voltage MOS devices.

16. The feedback control circuit of claim 10, wherein the divider circuit of the sense amplifier is a divide-by-three circuit.

17. The feedback control circuit of claim 10, wherein the divider circuit of the sense amplifier is a resistive circuit.

18. The feedback control circuit of claim 10, having all components realized in an integrated circuit (IC).