Synchronizing circuits and methods for parallel path analog-to-digital converters

• US 6,784,821 B1
• Filed: 10/20/2003
• Issued: 08/31/2004
• Est. Priority Date: 02/11/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Soo-Hyoung
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/689,435
• Publication Number:
  US 20040155806A1
• Time in Patent Office: 316 Days
• Field of Search: 341/155, 341/159, 341/101
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/141 in which at least one step is of the folding type; Folding stages therefore
• CPC Class Codes: H03M 1/203 using an analogue interpolation circuit
• CPC Class Codes: H03M 1/368 having a single comparator per bit, e.g. of the folding type

Abstract

An Analog-to-Digital (A/D) converter includes signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal. A respective signal path includes a comparator. A synchronizing circuit is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator. A respective signal path also includes a respective decoder that is responsive to a respective comparator and to the clock signal.

Claims

1. An analog-to-digital (A/D) converter, comprising:

a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital output signal therefrom; and

a circuit that is configured to generate delayed clock signals, which have delay times different from each other according to phase differences, by feeding-back and detecting a phase of signals in the signal paths, and configured to correct the signals in the signal paths by using the delayed clock signals.

2. An analog-to-digital (A/D) converter, comprising:

a clock buffer that is configured to receive and buffer an external clock signal, to thereby generate an internal clock signal;

a plurality of process routines that are configured to receive and process an analog input signal;

a plurality of comparators that are configured to receive analog signals from the plurality of process routines and to compare the received analog signals with a reference voltage, to thereby generate digital signals therefrom under control of a respective one of delayed clock signals;

a plurality of decoders that are configured to receive the digital signals from the plurality of comparators and to convert the received digital signals into a code format, to thereby generate converted digital signals; and

a synchronizing circuit that is configured to receive the internal clock signal from the clock buffer and the digital signals from the plurality of comparators and to generate the respective delayed clock signals therefrom.

3. An A/D converter according to claim 2, wherein the synchronizing circuit comprises:

a phase detector that is configured to receive the digital signals from the plurality of comparators, and to detect a phase difference between the digital signals;

a delay controller that is configured to receive an output signal of the phase detector, and to generate a respective time delay control signal for a respective one of the process routines, corresponding to the phase difference; and

a plurality of delay chain parts that are configured to receive the internal clock signal from the clock buffer and to generate the respective delayed clock signals, under control of a respective one of the time delay control signals.

4. An A/D converter according to claim 3, wherein the delay controller is comprised of a plurality of shift registers.

5. An A/D converter according to claim 2, wherein the plurality of process routines are comprised of folding/interpolation and/or flash process routines.

6. An A/D converter according to claim 3, wherein the plurality of process routines are comprised of folding/interpolation and/or flash process routines.

7. An analog-to-digital (A/D) converter, comprising:

a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom, a respective signal path including therein a comparator; and

a synchronizing circuit that is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator.

8. An A/D converter according to claim 7 wherein the respective signal path also includes therein a respective decoder that is responsive to the respective comparator and to the clock signal.

9. An A/D converter according to claim 7 wherein the synchronizing circuit is configured to generate the respective delayed clock signal based on at least one phase difference between the outputs of the comparators.

10. An A/D converter according to claim 8 wherein the synchronizing circuit is configured to generate the respective delayed clock signal based on at least one phase difference between the outputs of the comparators.

11. A synchronizing method for an analog-to-digital (A/D) converter that includes a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom, a respective signal path including therein a comparator, the synchronizing method comprising:

generating a plurality of delayed clock signals from a clock signal and outputs of the comparators; and

applying a respective one of the delayed clock signals to a respective comparator.

12. A method according to claim 11 wherein the respective signal path also includes therein a respective decoder that is responsive to the respective comparator, the method further comprising:

applying the clock signal to the respective decoders.

13. A method according to claim 11 wherein generating the plurality of delayed clock signals comprises generating the plurality of delayed clock signals based on at least one phase difference between the outputs of the comparators.

14. A method according to claim 12 wherein generating the plurality of delayed clock signals comprises generating the plurality of delayed clock signals based on at least one phase difference between the outputs of the comparators.