Analog-to-digital converter which is substantially independent of capacitor mismatch

• US 6,784,824 B1
• Filed: 08/29/2002
• Issued: 08/31/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh V
• Application Number:
  US10/231,541
• Time in Patent Office: 733 Days
• Field of Search: 341/118, 341/120, 341/155, 341/172
• US Class Current: 341/172
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

A method, apparatus, and system for providing accurate level shifting, residue multiplication, and sample-and-hold functions for ADCs, while eliminating capacitor mismatch as a source of ADC errors. An input signal is sampled onto a first capacitor, and the complemented input signal is sampled onto a second capacitor. The sampled input signal is provided to a first input terminal of a unity gain amplifier by controllably connecting the first capacitor between the amplifier output and the first input terminal. An inverted version of the sampled complemented input signal is level shifted and provided to the amplifier'"'"'s second input terminal by controllably coupling the second capacitor between a selected level-shift voltage and the second input terminal. The sampled analog input signal is added to the inverted version of the sampled complemented analog input signal, while subtracting the selected level-shift voltage, to provide a residue signal available for use in subsequent conversion stages.

Claims

1. An analog-to-digital converter (ADC) stage for use in ADCs, comprising:

an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal;

first and second capacitances coupled to sample an input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;

a level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of reference voltages in response to a second clock signal;

a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to the second clock phase;

a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the second capacitance to the selected reference voltage in response to the second clock phase;

wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected reference voltage to create the analog ADC residue signal for use in a subsequent ADC stage.

2. The ADC stage as in claim 1, wherein the level shifting circuit comprises:

a sub-ADC coupled to receive the input voltage signal, and to provide a digital code based on a voltage of the input voltage signal;

a decoder circuit coupled to the sub-ADC to receive the digital code and to assert one of a plurality of switch signals in response thereto; and

a plurality of switches, each coupled to a different one of the plurality of reference voltages; and

wherein the asserted one of the switch signals closes a corresponding one of the plurality of switches to couple a corresponding one of the plurality of reference voltages to the second capacitance to add to the inverted version of the sampled complemented input voltage.

3. The ADC stage as in claim 2, wherein the digital code is an n-bit binary code having 2ⁿ possible values, and wherein each of the 2ⁿ possible values enables a different one of the plurality of switch signals to be asserted by the decoder circuit.

4. The ADC stage as in claim 2, wherein the digital code is a 1.5-bit binary code having three possible values, and wherein each of the three possible values enables a different one of the plurality of switch signals to be asserted by the decoder circuit.

5. The ADC stage as in claim 1, wherein:

the first capacitance comprises at least one capacitor having a top plate and a bottom plate;

the top plate of the capacitor is coupled to a first reference voltage via the first switch circuit during the first clock phase, and to the first input terminal of the amplifier via the first switch circuit during the second clock phase; and

the bottom plate of the capacitor is coupled to the input voltage signal through the first switch circuit during the first clock phase, and to the output terminal of the amplifier via the first switch circuit during the second clock phase.

6. The ADC stage as in claim 1, wherein:

the second capacitance comprises at least one capacitor having a top plate and a bottom plate;

the top plate of the capacitor is coupled to a second reference voltage via the second switch circuit during the first clock phase, and to the second input terminal of the amplifier via the second switch circuit during the second clock phase; and

the bottom plate of the capacitor is coupled to the complemented input voltage signal through the second switch circuit during the first clock phase, and to the reference voltage selected by the level shifting circuit via the second switch circuit during the second clock phase.

7. The ADC stage as in claim 1, further comprising a reset circuit coupled to the amplifier to discharge residual charge present at one or more of the first and second input terminals and output terminal of the amplifier to clear a current analog ADC residue signal in preparation for output of a subsequent analog ADC residue signal.

8. The ADC stage as in claim 7, wherein the reset circuit comprises a plurality of switches each coupled between a reference voltage and a different one of the first input terminal, second input terminal, and output terminal.

9. The ADC stage as in claim 8, wherein the reset circuit further comprises a switch coupled between the first and second input terminals.

10. The ADC stage as in claim 9, wherein each of the switches is closed in response to the first clock phase to enable the residual charge to be discharged to the reference voltage.

11. The ADC stage as in claim 1, wherein the first and second capacitance comprise first and second capacitor components that are substantially electrically isolated from each other via an impedance between the first and second input terminals of the amplifier.

12. The ADC stage as in claim 1, further comprising an inverter coupled to receive the input voltage signal and to generate the complemented input voltage signal.

13. The ADC stage as in claim 1, wherein the input voltage signal and complemented input voltage signal comprise complementary input voltage signals of a differential input voltage signal.

14. The ADC stage as in claim 1, wherein the amplifier is a single-ended operational amplifier.

15. The ADC stage as in claim 1, further comprising:

third and fourth capacitances coupled to sample the input voltage signal and the complemented input voltage signal respectively in response to the second clock phase;

a second level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of second reference voltages in response to the first clock phase;

a third switch circuit coupled to the third capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the third capacitance via a second feedback loop, in response to the first clock phase;

a fourth switch circuit coupled to the fourth capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the fourth capacitance to the selected second reference voltage in response to the first clock phase;

wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected second reference voltage to create a second analog ADC residue signal for use in a subsequent ADC stage.

16. A method for converting an analog input signal to a digital signal using an amplifier, the method comprising:

(a) sampling the analog input signal onto a first capacitor and a complement of the analog input signal onto a second capacitor;

(b) providing the sampled analog input signal at a first input terminal of the amplifier by controllably coupling the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration;

(c) providing the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected one of the reference voltages and the second input terminal of the amplifier; and

(d) adding the sampled analog input signal to an inverted version of the sampled complemented analog input signal and subtracting the selected one of the reference voltages to provide a residue signal available for use in subsequent conversion stages.

17. The method of claim 16, further comprising repeating steps (a)-(d) for each of the first M−

1 stages of an M-stage analog-to-digital conversion having an N-bit resolution.

18. The method of claim 17, further comprising resolving least significant bits of the digital signal in an M-th flash stage of the analog to digital conversion, by comparing the residue signal from the M−

1 stage to a set of predetermined reference voltages.

19. The method of claim 18, wherein the set of predetermined reference voltages comprises 2ⁿ=1 reference voltages, wherein n corresponds to a resolution of the M-th stage.

20. The method of claim 19, further comprising resolving N−

M bits at the M-th stage of the analog-to-digital conversion having the N-bit resolution.

21. The method of claim 16, wherein the analog input signal and the complemented analog input signal comprise two signals of a differential signal pair.

22. The method of claim 16, further comprising inverting the analog input signal create the complemented analog input signal.

23. The method of claim 16, further comprising providing a multi-phase clock signal including a first clock phase and a second clock phase, and wherein step (a) is performed during the first clock phase and steps (b), (c), and (d) are performed during the second clock phase.

24. The method of claim 23, wherein controllably coupling the first capacitor between the amplifier output and the first input terminal comprises activating one or more switches coupled between the amplifier output and the first input terminal to complete a circuit path therebetween in response to a transition of the second clock phase.

25. The method of claim 24, further comprising activating one or more sampling switches coupled between the analog input signal and a reference voltage in response to a first transition of the first clock phase, and deactivating the sampling switches in response to a second transition of the first clock phase.

26. The method of claim 23, wherein controllably coupling the second capacitor between a selected one of the reference voltages and the second input terminal of the amplifier comprises activating one or more switches coupled between the selected one of the reference voltages and the second input terminal of the amplifier to complete a circuit path therebetween in response to a transition of the second clock phase.

27. The method of claim 26, further comprising activating one or more sampling switches coupled between the selected one of the reference voltages and the second input terminal of the amplifier in response to a first transition of the first clock phase, and deactivating the sampling switches in response to a second transition of the first clock phase.

28. An analog-to-digital converter (ADC) stage for use in converting a differential analog input signal to a digital signal, comprising:

a first single-ended amplifier arranged in a unity feedback configuration;

first and second sampling means for sampling the differential analog input signal at a first time;

first switch means coupled to the first and second sampling means and to the first amplifier for providing the sampled differential analog input signal to first and second input terminals of the first amplifier, and to provide a level-shift voltage to offset the sampled differential analog input signal at the second input terminal of the first amplifier, at a second time;

a second single-ended amplifier arranged in a unity feedback configuration;

third and fourth sampling means for sampling the differential analog input signal at the first time;

second switch means coupled to the third and fourth sampling means and to the second amplifier for providing the sampled differential analog input signal to first and second input terminals of the second amplifier, and to provide a level-shift voltage to offset the sampled differential analog input signal at the second input terminal of the second amplifier; and

wherein the first and second amplifiers respectively add the respective sampled differential analog input signals and subtract the level-shift voltage, and collectively output a differential output signal at the second time.

29. An analog-to-digital converter (ADC) stage for use in differential ADCs, comprising:

(a) a first sample and hold circuit, comprising;

(1) a first single-ended amplifier having first and second input terminals, and an output terminal to output a first half of a differential residue signal;

(2) a first sampling circuit comprising first and second capacitors to respectively store first and second voltages of a differential input signal at a first time;

(3) a first switch circuit coupled to the first amplifier and to the first sampling circuit to switch the first capacitor between the first amplifier'"'"'s output terminal and its first input terminal, and to switch the second capacitor between a selectable level-shift voltage and the first amplifier'"'"'s second input terminal;

(4) wherein the first amplifier adds the first and second voltages, subtracts a selected one of the selectable level-shift voltages, and outputs the first half of the differential residue signal at a second time;

(b) a second sample and hold circuit, comprising;

(1) a second single-ended amplifier having first and second input terminals, and an output terminal to output a second half of the differential residue signal;

(2) a second sampling circuit comprising third and fourth capacitors to respectively store the second and first voltages of the differential input signal at the first time;

(3) a second switch circuit coupled to the second amplifier and to the second sampling circuit to switch the third capacitor between the second amplifier'"'"'s output terminal and its first input terminal, and to switch the fourth capacitor between the selectable level-shift voltage and the second amplifier'"'"'s second input terminal; and

(4) wherein the second amplifier adds the second and first voltages, subtracts a selected one of the selectable level-shift voltages, and outputs the second half of the differential residue signal at the second time.

30. An algorithmic analog-to-digital converter (ADC) to convert an input voltage signal to a digital data signal, comprising:

(a) an ADC stage to receive the input voltage signal and to create an analog ADC residue signal, the ADC stage comprising;

(1) an amplifier having first and second input terminals, and an output terminal;

(2) first and second capacitances coupled to sample the input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;

(3) a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase;

(4) a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase;

(5) a sub-ADC circuit coupled to receive the input voltage signal, and in response, to provide a digital data subset of the digital data signal;

(6) a decoder coupled to the sub-ADC circuit to receive the digital data subset and to select one of a plurality of reference voltages to add to the inverted version of the complemented input voltage in response thereto;

(7) wherein the amplifier outputs the analog ADC residue signal by adding the sampled input voltage signal to the inverted version of the sampled complemented input voltage as shifted by the level shifting circuit; and

(b) a feedback loop to provide the analog ADC residue signal as the input voltage signal to the ADC stage for N−

1 additional cycles of an N-cycle analog-to-digital conversion.

31. The algorithmic ADC as in claim 30, further comprising a final flash stage coupled to the ADC stage to receive the analog ADC residue signal from the ADC stage corresponding to the N−

1 cycle of the N-cycle analog-to-digital conversion, and to provide a least significant digital data subset of the digital data signal.

32. The algorithmic ADC as in claim 31, further comprising an accumulation circuit to accumulate each of the digital data subsets to create the digital data signal.

33. The algorithmic ADC as in claim 32, wherein the accumulation circuit comprises a digital error correction (DEC) circuit to add together each of the digital data subsets and to concatenate the least significant digital data subset to create the digital data signal.

34. A pipelined analog-to-digital converter (ADC) to convert an input voltage signal to a digital data signal, comprising:

(a) a plurality of N−

1 pipelined ADC stages, wherein a first pipelined ADC stage receives the input voltage signal, and the remaining N−

1 pipelined ADC stages receive an analog ADC residue signal from a prior ADC stage as its input voltage signal, each of the plurality of ADC stages comprising;

(1) an amplifier having first and second input terminals, and an output terminal;

(2) first and second capacitances coupled to sample the input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;

(3) a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase;

(4) a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase;

(5) a sub-ADC circuit coupled to receive the input voltage signal, and in response, to provide a digital data subset of the digital data signal;

(6) a decoder coupled to the sub-ADC circuit to receive the digital data subset and to select one of a plurality of reference voltages to add to the inverted version of the complemented input voltage in response thereto;

(7) wherein the amplifier outputs the analog ADC residue signal by adding the sampled input voltage signal to the inverted version of the sampled complemented input voltage as shifted by the level shifting circuit; and

(b) an Nth pipelined ADC stage coupled to the N−

1 ADC stage to resolve least significant bits of the digital data signal.