Universal two dimensional (frame and line) timing generator

• US 6,784,929 B1
• Filed: 08/20/1999
• Issued: 08/31/2004
• Est. Priority Date: 08/20/1999
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Chen, Tai-Ming
• Primary Examiner(s): Christensen, Andrew
• Assistant Examiner(s): GENCO, BRIAN C
• Application Number:
  US09/378,183
• Time in Patent Office: 1,838 Days
• Field of Search: 348/312, 348/230.1, 348/317, 377/63, 377/52, 377/57, 345/213, 345/545
• US Class Current: 348/230.1
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals

Abstract

A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined waveform control word for both waveform generator control units. The SRAM data is entered via the host controller external data bus. A single waveform control word may be used to control both waveform generators.

Claims

1. A timing generator for an imaging system, characterized by:

a line control unit configured to generate a first timing waveform for line read out of image data from an image sensor;

a frame control unit coupled to the line control unit and configured to generate a second timing waveform for frame read out of image data from an image sensor, the frame control unit including a next frame control word register and a current frame control word register, the next frame control word register to buffer a next frame control word, the current frame control word register to buffer a current frame control word;

a clock generator configured to provide a clock signal to the line control unit;

a request arbitrator configured to arbitrate timing requests between the line control unit and the frame control unit based on an input; and

a control word memory coupled to the request arbitrator and configured to provide a line control word to the line control unit or a frame control word to the frame control unit depending on an output from the request arbitrator, the line control word and the frame control word to control the first timing waveform and the second timing waveform, respectively,

wherein the next frame control word register and the current frame control word register provide the input.

2. A timing generator according to claim 1, wherein the line control word for the line control unit and the frame control word for the frame control unit are of a same size.

4. A timing generator according to claim 1, wherein a portion of the next frame control word register and a portion of the current frame control word register is used to provide the input.

5. A timing generator according to claim 1, the line control unit including a current line control word register.

6. A timing generator according to claim 1, the arbitrator providing the line control unit higher priority over the frame control unit.

20. A timing generator according to claim 1, wherein the frame control unit further includes a next frame control word empty register configured to indicate when the next frame control word register is empty, the next frame control word empty register to provide an additional input for the input to the request arbitrator.

21. A timing generator according to claim 20, wherein the input to the request arbitrator includes a timing request from the frame control unit or the line control unit.

3. A timing generator, characterized by:

a line control unit configured to generate a first timing waveform;

a frame control unit coupled to the line control unit and configured to generate a second timing waveform;

a clock generator configured to provide a clock signal to the line control unit, the clock generator including first and second reload registers coupled to provide inputs to a multiplexer, the multiplexer pro viding an output to a down counter, the down counter coupled to provide a clock output;

a request arbitrator configured to arbitrate timing requests between the line control unit and the frame control unit; and

a control word memory coupled to the request arbitrator and configured to provide a control word to the line control unit or the frame control unit depending on an output from the request arbitrator.

7. An imaging sensing system, characterized by:

an image sensor for temporarily buffering image data;

a data buffer for temporarily buffering the image data; and

a timing generator, the timing generator including;

a line control unit configured to generate a first timing waveform for line read out of the image data from the image sensor;

a frame control unit coupled to the line control unit and configured to generate a second timing waveform for frame read out of the image data from the image sensor, the frame control unit including a next frame control word register and a current frame control word register, the next frame control word register to buffer a next frame control word, the current frame control word register to buffer a current frame control word;

a clock generator configured to provide a clock signal to the line control unit;

a request arbitrator configured to arbitrate timing requests between the line control unit and the frame control unit based on an input; and

a control word memory coupled to the request arbitrator and configured to provide a line control word to the line control unit or a frame control word to the frame control unit depending on an output from the request arbitrator, the line control word and the frame control word to control the first timing waveform and the second timing waveform, respectively.

wherein the next frame control word register and the current frame control word register provide the input.

8. An imaging sensing system according to claim 7, wherein the line control word for the line control unit and the frame control word for the frame control unit are of a same size.

10. An imaging system according to claim 7, wherein a portion of the next frame control word register and a portion of the current frame control word register is used to provide the input.

11. An imaging sensing system according to claim 7, the line control unit including a current line control word register.

12. An imaging sensing system according to claim 7, the arbitrator providing the line control unit higher priority over the frame control unit.

22. An imaging sensing system according to claim 7, wherein the frame control unit further includes a next frame control word empty register configured to indicate when the next frame control word register is empty, the next frame control word empty register to provide an additional input for the input to the request arbitrator.

23. An imaging sensing system according to claim 22, wherein the input to the request arbitrator includes a timing request from the frame control unit or the line control unit.

9. An imaging sensing system, characterized by:

an image sensor for temporarily buffering image data;

a data buffer for temporarily buffering the image data; and

a timing generator, the timing generator including,

a line control unit configured to generate a first timing waveform for line read out of the image data from the image sensor;

a frame control unit coupled to the line control unit and configured to generate a second timing waveform for frame read out of the image data from the image sensor;

a clock generator configured to provide a clock signal to the line control unit, the clock generator including first and second reload registers coupled to provide inputs to a multiplexer, the multiplexer providing an output to a down counter, the down counter coupled to provide a clock output,

a request arbitrator configured to arbitrate timing requests between the line control unit and the frame control unit; and

a control word memory coupled to the request arbitrator and configured to provide a control word to the line control unit or the frame control unit depending on an output from the request arbitrator.

13. A timing generator for an imaging system, characterized by:

a line control unit configured to generate a first timing waveform for line read out of image data from an image sensor;

a frame control unit coupled to the line control unit and configured to generate a second timing waveform for frame read out of image data from an image sensor, the frame control unit including a next frame control word register and a current frame control word register, the next frame control word register to buffer a next frame control word, the current frame control word register to buffer a current frame control word;

a control word memory configured to provide a line control word to the line control unit or a frame control word to the frame control unit, the line control word and the frame control word to control the first timing waveform and the second timing waveform, respectively; and

an arbitration unit coupled to the line control unit, the frame control unit, and the control word memory, the arbitration unit configured to select which one of the line control unit or the frame control unit is active based on an input,

wherein the next frame control word register provide and the current frame control word register the input.

14. A timing generator according to claim 13, wherein the line control word for the line control unit and the frame control word for the frame control unit are of a same size.

15. A timing generator according to claim 13, further including a clock generator coupled to the line control unit.

17. A timing generator according to claim 13, wherein a portion of the next frame control word register and a portion of the current frame control word register is used to provide the input.

18. A timing generator according to claim 13, the line control unit including a current line control word register.

19. A timing generator according to claim 13, the arbitration unit providing the line control unit higher priority over the frame control unit.

24. A timing generator according to claim 13, wherein the frame control unit further includes a next frame control word empty register configured to indicate when the next frame control word register is empty, the next frame control word empty register to provide an additional input for the input to the arbitration unit.

25. A timing generator according to claim 24, wherein the input to the arbitration unit includes a timing request from the frame control unit or the line control unit.

16. A timing generator, characterized by:

a control word memory configured to provide a control word for a line control unit for outputting a first waveform and a frame control unit for outputting a second waveform;

an arbitration unit coupled to the line control unit, the frame control unit, and the control word memory, the arbitration unit configured to select which one of the line control unit or the frame control unit is active; and

a clock generator coupled to the line control unit, the clock generator including first and second reload registers coupled to provide inputs to a multiplexer, the multiplexer providing an output to a down counter, the down counter coupled to provide a clock output.