Power sequence protection for a level shifter

• US 6,785,107 B1
• Filed: 06/22/2001
• Issued: 08/31/2004
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Schmitt, Jonathan
• Primary Examiner(s): Sircus, Brian
• Assistant Examiner(s): Nguyen, Danny
• Application Number:
  US09/888,207
• Time in Patent Office: 1,166 Days
• Field of Search: 361/90, 361/91.1, 361/92, 327/108, 327/333
• US Class Current: 361/91.1
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.

Claims

1. A power sequence protection circuit comprising:

a latch electrically coupled to an input voltage supply and an output voltage supply; and

a switch electrically coupled to the latch wherein the latch sets the switch to a first state for holding a level shifter in a pre-selected state if the output voltage supply is powered on when the input voltage supply is not powered on and wherein the latch sets the switch to a second state for releasing the level shifter from the pre-selected state when the input voltage supply and the output voltage supply are powered on.

2. The power sequence protection circuit of claim 1 wherein the switch connects a common voltage rail to an output signal port or an inverted output signal port of the level shifter in the first state.

3. The power sequence protection circuit of claim 2 wherein the switch presents a high impedance to the output signal port or the inverted output signal port of the level shifter in the second state.

4. The power sequence protection circuit of claim 1 further comprising the level shifter.

5. A power sequence protection circuit comprising:

a switch connected to a level shifter between an output signal port or an inverted output signal port of the level shifter and a common voltage rail; and

a latch connected to the switch to drive the switch to a conducting state if an input voltage supply is not powered on when an output voltage supply is powered on and to drive the switch to a non-conducting state if the input voltage supply and the output voltage supply are powered on.

6. The power sequence protection circuit of claim 5 wherein the switch comprises two field effect transistors connected in series.

7. The power sequence protection circuit of claim 5 wherein the latch comprises two field effect transistors connected in series between a third field effect transistor and the common voltage rail.