Semiconductor memory device having a memory cell structure of reduced occupying area

• US 6,785,157 B2
• Filed: 04/10/2002
• Issued: 08/31/2004
• Est. Priority Date: 05/21/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/119,094
• Publication Number:
  US 20020172070A1
• Time in Patent Office: 874 Days
• Field of Search: 365/149, 365/189.09, 365/233, 365/230.01
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells arranged in row and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data;

a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;

a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs; and

row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line.

2. The semiconductor memory device according to claim 1, wherein said row selecting circuitry drives two word lines simultaneously into a selected state in accordance with said address signal.

3. The semiconductor memory device according to claim 1, wherein two bit lines are arranged per pitch of the memory cells in a row direction, and

said row selecting circuitry simultaneously selects two word lines with a non-selected word line interposed in between.

4. The semiconductor memory device according to claim 1, wherein the cell plate electrodes are formed under the bit lines.

5. The semiconductor memory device according to claim 1, wherein active areas for forming the memory cells are arranged in alignment in a direction of the columns.

6. The semiconductor memory device according to claim 1, wherein active areas for forming the memory cells are arranged in a column direction with staggering of ½

of a pitch of an arrangement interval in a row direction of the memory cells.

7. The semiconductor memory device according to claim 1, wherein said row selecting circuitry selects one word line out of the word lines in accordance with the address signal.

8. The semiconductor memory device according to claim 1, wherein active areas for forming the memory cells are arranged continuously extending along a column direction.

9. The semiconductor memory device according to claim 1, wherein said cell plate electrode is kept in an electrically floating state.

10. The semiconductor memory device according to claim 1, wherein the bit lines in each pair have a crossing section.

11. The semiconductor memory device according to claim 1, wherein

the cell plate electrode receives a predetermined voltage, and

said row selecting circuitry drives said addressed word line into a voltage level equal to a voltage of said cell plate electrode.

20. The semiconductor memory device according to claim 1, wherein each memory cell is electrically isolated from adjacent memory cells thereto by means of an insulating film formed in a bottom of a cell isolating region of a trench structure, and

each cell plate electrode comprises an electrode layer formed on a side wall of the trench.

12. A semiconductor memory device, comprising:

a plurality of memory cells, arranged in rows and columns, each including a capacitor including a cell plate electrode for receiving a reference voltage and a storage electrode for accumulating electric charges corresponding to storage data;

a plurality of word lines, arranged corresponding to the rows of the memory cells, each connecting to the memory cells on a corresponding row, each word line comprising an interconnection line formed in a first lower interconnection layer different from and below a second interconnection layer of the cell plate electrode, and arranged adjacently to said cell plate electrode; and

a plurality of bit lines, arranged corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column, the bit lines being formed above the word lines and the cell plate electrode, the memory cells being arranged such that two memory cells aligned in a column direction shares a contact to a corresponding bit, the memory cells adjacent in a row direction are simultaneously connected to corresponding bit lines, and the memory cells connected to a pair of bit lines adjacent to each other constitute a unit for storing 1-bit data.

13. The semiconductor memory device according to claim 12, wherein the cell plate electrode is arranged extending in the row direction and corresponding to the memory cells arranged in alignment in two rows, and word lines arranged corresponding to the memory cells aligned in the two rows are arranged between the cell plate electrodes adjacent to each other.

14. The semiconductor memory device according to 12, wherein each cell plate electrode is arranged corresponding to each respective memory cell row.

15. The semiconductor memory device according to claim 12, wherein said first interconnection layer is a polysilicon interconnection layer containing an impurity implanted to a semiconductor substrate region below the first interconnecting layer for adjusting a threshold voltage and formed through dual polysilicon gate process, and said second interconnection layer is made of an impurity implanted polysilicon interconnection layer an impurity implanted independently of the impurity implanted to said semiconductor substrate region.

16. The semiconductor memory device according to claim 12, wherein said cell plate electrode is arranged in a meshed shape, extending over the area where the memory cells are arranged.

17. A semiconductor memory device, comprising:

a plurality of memory cells, arranged in rows and columns, each including a capacitor including a cell plate electrode and a storage electrode layer for accumulating electric charges corresponding to storage data, said storage electrode layer being formed facing to said cell plate electrode in a surface of a semiconductor substrate region;

a plurality of word lines, arranged corresponding to the rows of memory cells, each connecting to the memory cells on a corresponding row;

word line selection circuitry for selecting a word line arranged corresponding to an addressed row in accordance with an address signal; and

cell plate voltage control circuitry for changing a voltage of the cell plate electrode to a first reference voltage level in synchronization with transition of the selected word line into a non-selected state upon completion of an access cycle for selecting a memory cell, and changing said first reference voltage to a second reference voltage level at the time of start of the access cycle.

18. The semiconductor memory device according to claim 17, wherein said first reference voltage is a ground voltage level, and said second reference voltage level is at a level of a high level voltage of bit lines.

19. The semiconductor memory device according to claim 17, further comprising a plurality of bit lines, arranged corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column,

wherein each of the memory cells further comprises an impurity region formed adjacently to said storage electrode layer in the surface of said semiconductor substrate region, and said impurity region is electrically connected to a corresponding bit line when a corresponding word line is selected.