Combination etch stop and in situ resistor in a magnetoresistive memory and methods for fabricating same

• US 6,785,159 B2
• Filed: 08/29/2002
• Issued: 08/31/2004
• Est. Priority Date: 08/29/2002
• Status: Expired due to Term

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, Mark E.
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/231,803
• Publication Number:
  US 20040042261A1
• Time in Patent Office: 733 Days
• Field of Search: 365/158, 365/171
• US Class Current: 365/158
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: H01F 41/308 lift-off processes, e.g. ion milling, for trimming or patterning
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

Magnetic memory elements and methods for forming the same, where a magnetic memory element includes an etch stop layer disposed between a lower electrode and a magnetoresistive cell body or stack. The etch stop layer advantageously protects the lower electrode during patterning of the magnetoresistive cell body. The etch stop layer can be patterned with patterning of the magnetoresistive cell body. The etch stop layer can be formed from conductive materials or from resistive materials. When the etch stop layer is formed from resistive materials, the etch stop layer forms an in situ resistor that can isolate a failed memory cell from other memory cells in a corresponding array of cells, such as in an MRAM. This permits the MRAM to continue to utilize other magnetoresistive cells that are coupled to the electrodes in the event of a failure of the magnetoresistive cell.

Claims

1. A method of fabricating a portion of a magnetic memory device, the method comprising:

providing a substrate assembly with an insulating material, where the substrate assembly includes an electrode in a trench, where an upper surface of the electrode is substantially flush with an upper surface of the insulating material;

forming an etch stop layer on the upper surface of the substrate assembly, where a material for the etch stop layer is not ferromagnetic;

forming a magnetoresistive stack of layers, where the magnetoresistive stack of layers includes at least a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer;

forming a mask pattern on top of the magnetoresistive stack of layers;

patterning the magnetoresistive stack of layers and at least a portion of the etch stop layer with a first etchant to define MRAM cells; and

patterning with a second etchant after patterning with the first etchant, where patterning with the second etchant removes selected portions of the etch stop layer.

2. The method as defined in claim 1, wherein patterning with the second etchant is performed prior to patterning with the first etchant.

3. The method as defined in claim 1, wherein patterning with the second etchant is performed after patterning with the first etchant.

4. The method as defined in claim 3, wherein patterning with the first etchant comprises an anisotropic etching and patterning with the second etchant comprises selective chemical etching.

5. The method as defined in claim 1, wherein the material of the etch stop layer comprises titanium aluminum nitride (TiAlN).

6. The method as defined in claim 5, wherein the etch stop layer has a thickness in a range between about 100 Angstroms (Å

) and 500 Å

.

7. The method as defined in claim 1, wherein the material of the etch stop layer comprises at least one of tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

8. The method as defined in claim 1, wherein the material of the etch stop layer comprises at least one of tantalum (Ta), aluminum, titanium, and tungsten.

9. The method as defined in claim 1, wherein patterning comprises removing portions of the etch stop layer such that the etch stop layer is discontinuous between the electrode and an adjacent electrode.

10. A method of fabricating a portion of a magnetic memory device, the method comprising:

providing a substrate assembly with a copper electrode in a trench;

forming a layer of titanium aluminum nitride (TiAlN) on the upper surface of the substrate assembly;

forming a magnetoresistive stack of layers, where the magnetoresistive stack of layers includes at least a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer;

forming a mask pattern on top of the magnetoresistive stack of layers; and

patterning the magnetoresistive stack of layers to define MRAM cells.

11. The method as defined in claim 10, further comprising forming the titanium aluminum nitride (TiAlN) layer to a thickness in a range between about 100 Angstroms (Å

) and 200 Å

.

12. The method as defined in claim 10, wherein patterning the magnetoresistive stack of layers comprises a reactive ion etch (RIE) process.

13. The method as defined in claim 12, further comprising removing the etch stop layer by forming a second mask pattern on top of the magnetoresistive stack of layers and patterning the etch stop layer with the second mask pattern.

14. The method as defined in claim 13, further comprising removing the etch stop layer before patterning of the magnetoresistive stack of layers that defines MRAM cells.

15. A method of fabricating a portion of a magnetic memory device, the method comprising:

providing an electrode in a trench of an insulating layer, where an upper surface of the electrode is substantially flush with the upper surface of the substrate assembly;

forming an etch stop layer on at least the upper surface of the electrode, where a material for the etch stop layer is not ferromagnetic;

forming a magnetoresistive stack of layers, where the magnetoresistive stack of layers includes at least a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer;

forming a mask pattern on top of the magnetoresistive stack of layers;

patterning with a first etchant, where the first etchant is selected to remove portions of the magnetoresistive stack of layers that are not protected by the mask pattern, where patterning with the first etchant defines MRAM cells; and

patterning with a second etchant to remove at least a portion of the etch stop layer.

16. The method as defined in claim 15, wherein the electrode comprises copper, the etch stop layer comprises titanium aluminum nitride (TiAlN), the first etchant comprises a chlorine-based etchant, and the second etchant comprises a fluorine-based etchant.

17. The method as defined in claim 15, wherein the first etchant comprises a directional etchant and the second etchant comprises a non-directional selective etch.

18. The method as defined in claim 15, wherein patterning with the first etchant removes at least a portion of the etch stop layer and patterning with the second etchant removes remaining portions of the etch stop layer from select areas of the substrate assembly.

19. The method as defined in claim 15, wherein the same mask pattern is used while patterning with the first etchant and patterning with the second etchant.

20. The method as defined in claim 15, further comprising:

removing the mask pattern after patterning with the first etchant;

forming a second mask pattern on top of the substrate assembly, where the second mask pattern covers portions of the magnetoresistive stack of layers and portions of the etch stop layer; and

using the second mask pattern when patterning with the second etchant.

21. The method as defined in claim 15, the insulating material comprises silicon oxide (SiO₂), the electrode comprises copper (Cu), and where the second etchant is substantially non-corrosive at least to silicon dioxide (SiO₂) and to copper (Cu).

22. The method as defined in claim 15, wherein the second etchant removes material from the etch stop layer at a first rate and material from the electrode at a second rate, and where the second rate is slower than the first rate.

23. A method of fabricating an in-situ resistor in a magnetoresistive random access memory, the method comprising:

forming a layer of a resistive material on a substrate assembly;

forming a magnetoresistive stack on the layer of the resistive material; and

forming a layer of mask material on the magnetoresistive stack, where the layer of mask material defines openings to expose select portions of the magnetoresistive stack; and

etching through the openings of the mask material to define magnetic cells.

24. The method as defined in claim 23, wherein the resistive material comprises titanium aluminum nitride (TiAlN).

25. The method as defined in claim 23, wherein a thickness of the resistive material ranges from about 100 Angstroms (Å

) to about 500 Å

.

26. A method of providing partial isolation of a first magnetic memory cell in a memory array such that a failed memory cell can be isolated, the method comprising:

providing a first electrode that is coupled to a first group of magnetic memory cells, where the first magnetic memory cell is a member of the first group of magnetic memory cells;

providing a second electrode that is coupled to a second group of magnetic memory cells, where the first magnetic memory cell is also a member of the first group of magnetic memory cells; and

coupling the first magnetic memory cell to the first electrode and to the second electrode through an in situ resistor with a predetermined resistance of at least 100 ohms, where the in situ resistor is in series with the first magnetic memory cell, but not in series with other magnetic memory cells.

27. The method as defined in claim 26, wherein the in situ resistor is formed between the first electrode and the first magnetic memory cell by a layer of resistive material.

28. The method as defined in claim 27, where the resistive material comprises titanium aluminum nitride (TiAlN).

29. The method as defined in claim 27, where the resistive material comprises at least one of tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

30. The method as defined in claim 27, where the layer of resistive material extends the length of the first electrode.

31. An in situ resistor in a magnetoresistive memory cell comprising:

a first side coupled to an electrode in a damascene trench;

a second side coupled to a magnetoresistive cell; and

resistive material between the first side and the second side, and where the resistive material has a resistivity of at least 0.2 ohm-centimeters (Ω

-cm).

32. The in situ resistor as defined in claim 31, where the resistive material is titanium aluminum nitride (TiAlN).

33. The in situ resistor as defined in claim 31, where the resistive material comprises at least one of tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

34. The in situ resistor as defined in claim 31, where the resistive material comprises at least one of metal nitride, metal nitro-silicide, and metal alloy nitride.

35. The in situ resistor as defined in claim 31, where the resistive material is between about 100 angstroms (Å

) and about 500 Å

in thickness.

36. A magnetoresistive memory cell comprising:

a lower electrode with an upper surface;

a magnetoresistive stack with a first end and a second end, where the magnetoresistive stack is oriented such that the first end of the magnetoresistive stack faces in the direction of the lower electrode, and where a cell body of the magnetoresistive stack corresponds to a first pattern;

an upper electrode coupled to the second end of the magnetoresistive stack; and

a resistive etch stop layer disposed at least between the upper surface of the lower electrode and the first end of the magnetoresistive stack.

37. The magnetoresistive memory cell as defined in claim 36, wherein the etch stop layer comprises titanium aluminum nitride (TiAlN).

38. The magnetoresistive memory cell as defined in claim 36, wherein the etch stop layer comprises at least one of tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

39. The magnetoresistive memory cell as defined in claim 36, wherein the etch stop layer comprises at least one of metal nitride, metal nitro-silicide, and metal alloy nitride.

40. The memory cell as defined in claim 36, where the lower electrode comprises copper, where the lower electrode is disposed within a trench of a dielectric material, and where an upper surface of the lower electrode is substantially coplanar with an upper surface of the dielectric material.

41. A magnetoresistive memory cell comprising:

a lower electrode with an upper surface, where the lower electrode is disposed within a trench of a dielectric material, where the upper surface of the lower electrode is substantially coplanar with an upper surface of the dielectric material;

a magnetoresistive stack with a first end and a second end, where the first end of the magnetoresistive stack faces in the direction of the lower electrode;

an upper electrode coupled to the second end of the magnetoresistive stack; and

an etch stop layer disposed at least between the upper surface of the lower electrode and the first end of the magnetoresistive stack, where an area of the etch stop layer is larger than the lower electrode such that a portion of the etch stop layer overlays the lower electrode and a portion of the upper surface of the dielectric material.

42. The magnetoresistive memory cell as defined in claim 41, where the etch stop layer comprises titanium aluminum nitride (TiAlN).

43. The magnetoresistive memory cell as defined in claim 41, where the etch stop layer comprises at least one of tantalum (Ta), aluminum, titanium, tungsten, tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

44. The magnetoresistive memory cell as defined in claim 41, wherein the etch stop layer comprises at least one of metal nitride, metal nitro-silicide, and metal alloy nitride.

45. The magnetoresistive memory cell as defined in claim 41, wherein the etch stop layer is further disposed between the upper surface of the lower electrode and a second magnetoresistive stack corresponding to an adjacent magnetoresistive memory cell.

46. A magnetoresistive random access memory (MRAM) device comprising:

a plurality of lower electrodes, each having an upper surface, where the lower electrodes are disposed within a plurality of trenches of a dielectric material, where the upper surfaces of the lower electrodes are substantially coplanar with an upper surface of the dielectric material;

a plurality of magnetoresistive cells each having a first end and a second end, where the first ends of magnetoresistive cells face in the direction of corresponding lower electrodes, and where cell bodies of the magnetoresistive cells correspond to a first pattern;

a plurality of upper electrodes coupled to the second ends of the magnetoresistive cells; and

a resistive etch stop layer with a plurality of isolated pieces, where the isolated pieces are disposed between the upper surfaces of the lower electrodes and the first ends of magnetoresistive cells, where at least one of the isolated pieces is disposed under at least one of the magnetoresistive cells.

47. The MRAM as defined in claim 46, wherein at least one of the isolated pieces is disposed under at least two adjacent magnetoresistive cells of a common lower electrode.

48. The MRAM as defined in claim 46, wherein each isolated piece is patterned with the first pattern such that there is one isolated piece for each magnetoresistive cell.

49. The MRAM as defined in claim 46, wherein the resistive etch stop layer comprises titanium aluminum nitride (TiAlN).

50. The MRAM as defined in claim 46, wherein the resistive etch stop layer comprises at least one of tantalum nitride (TaN), tungsten silicon nitride (WSiN), and tantalum silicon nitride (TaSiN).

51. The MRAM as defined in claim 46, wherein the resistive etch stop layer comprises at least one of metal nitride, metal nitro-silicide, and metal alloy nitride.

52. The MRAM as defined in claim 46, wherein portions of the resistive etch stop layer have been removed from at least parts of regions between adjacent lower electrodes such that there is substantially no electrical conductivity between adjacent lower electrodes through the resistive etch stop layer.

53. The MRAM as defined in claim 46, wherein the lower electrodes and the upper electrodes are arranged in a cross point configuration.