Reducing the effects of noise in non-volatile memories through multiple reads

• US 6,785,164 B2
• Filed: 05/16/2003
• Issued: 08/31/2004
• Est. Priority Date: 01/18/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Gonzalez, Carlos J., Guterman, Daniel C.
• Primary Examiner(s): Tran, M.
• Application Number:
  US10/439,508
• Publication Number:
  US 20030202403A1
• Time in Patent Office: 473 Days
• Field of Search: 365/185.2, 365/185.21, 365/185.18
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.

Claims

1. A method of writing a data value in a non-volatile memory, comprising:

altering the state of a storage element in the non-volatile memory;

subsequent to said altering the state of the storage element and prior to further altering the state of the storage element, comparing a plurality of times a parameter indicative of the resultant state of the storage element to a reference value indicative of the data value; and

determining whether to further alter the state of the storage element in response to said comparing a plurality of times.

2. The method of claim 1, wherein said storage element is a multi-state storage element.

3. The method of claim 2, wherein said comparing is performed using a digital numerical technique.

4. The method of claim 2, wherein the storage element is a charge storing device.

5. The method of claim 4, wherein the parameter is a current.

6. The method of claim 4, wherein the parameter is a voltage.

7. The method of claim 4, wherein the parameter is a time.

8. The method of claim 4, wherein the parameter is a frequency.

9. The method of claim 4, wherein the parameter is a magnetic property.

10. The method of claim 4, wherein the parameter is an optical property.

11. The method of claim 2, wherein said comparing comprises a peak detection method.

12. The method of claim 2, wherein said comparing comprises an analog filtered average detection.

13. The method of claim 2, wherein the non-volatile memory comprises a memory unit containing a plurality of storage elements including said storage element and a controller, and wherein the comparing is preformed by the controller.

14. The method of claim 2, wherein the non-volatile memory comprises a memory unit containing a plurality of storage elements including said storage element and a controller, and wherein the comparing is performed by the memory unit.

15. The method of claim 1, wherein said storage element is one of a plurality of storage elements in which data are written concurrently.

16. A non-volatile memory comprising:

an array of storage elements;

read circuitry coupled to the array to provide a parameter associated with the state of a cell contained therein;

a sense amplifier coupled to the read circuitry to determine the value of the parameter; and

averaging circuitry coupled to the sense amplifier for forming a composite value for the single cell formed from multiple independently determined values of the parameter supplied from the sense amplifier.

17. The memory of claim 16, wherein the parameter is a current level.

18. The memory of claim 16, wherein the parameter is a voltage level.

19. The memory of claim 16, wherein the parameter is a time.

20. The memory of claim 16, wherein the parameter is a frequency.

21. The memory of claim 16, wherein the parameter is a magnetic property.

22. The memory of claim 16, wherein the parameter is an optical property.

23. The memory of claim 16, wherein the averaging circuitry comprises an adder to produce a sum of the multiple independently determined values and a division circuit for dividing the sum by the number of independently determined values added to produce the sum.

24. The memory of claim 16, wherein the memory comprises a storage section that includes the array, read circuitry, and sense amplifier and a controller section that includes the averaging circuitry.

25. The memory of claim 24, wherein the controller section further includes a plurality of registers wherein the multiple independently determined values of the parameter supplied from the sense amplifier are stored prior to being supplied to the averaging circuitry.

26. The memory of claim 24, wherein the storage section further includes a plurality of registers wherein the multiple independently determined values of the parameter supplied from the sense amplifier are stored prior to being supplied to the averaging circuitry.

27. The memory of claim 16, wherein the memory comprises a controller section and a storage section, the storage section including the array, read circuitry, sense amplifier and the averaging circuitry.

28. The memory of claim 27, wherein the storage section further includes a plurality of registers wherein the multiple independently determined values of the parameter supplied from the sense amplifier are stored prior to being supplied to the averaging circuitry.

29. The memory of claim 16, further comprising:

programming circuitry coupled to the array for changing the state of the storage elements contained therein and coupled to the averaging circuitry for receiving the composite value, wherein the composite value is used during the verify phase of a programming process.