Fully synchronous pipelined RAM

• US 6,785,188 B2
• Filed: 01/28/2002
• Issued: 08/31/2004
• Est. Priority Date: 04/19/1996
• Status: Expired due to Fees

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Mick, John R.
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): NGUYEN, TUAN T
• Application Number:
  US10/059,899
• Publication Number:
  US 20020154548A1
• Time in Patent Office: 946 Days
• Field of Search: 365/233, 365/191
• US Class Current: 365/233.1
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Claims

1. A memory structure, comprising:

a memory array;

at least one address register, the at least one address register latching an address on a rising edge of a clock signal;

at least one data register, the at least one data register latching a data word on the rising edge of the clock signal;

a logic circuit coupled to the memory array, the at least one address register, and the at least one data register,

wherein, the logic circuit operates in a write operation such that a write address is presented to the at least one address register in a first write clock cycle and a write data word is presented to the at least one data register in a second clock cycle following the first write clock cycle by a predetermined number of clock cycles; and

wherein the logic circuit operates in a read operation such that a read address is presented in a first read clock cycle and a read data word corresponding to the read address is presented to an output buffer in a second read clock cycle following the first read clock cycle by the predetermined number of clock cycles.

2. The structure of claim 1, wherein the read operation may occur in the following clock cycle from the write operation.

3. The structure of claim 1, wherein a second read operation may occur in the following clock cycle from the read operation.

4. The structure of claim 1, wherein the write operation may occur in the following clock cycle from the read operation.

5. The structure of claim 1, wherein a second write operation may occur in the following clock cycle from the write operation.

6. The structure of claim 1, wherein the data word is stored in the at least one data registers for a predetermined number of write cycles and then written into the memory array.

7. The structure of claim 6, wherein the data word corresponding to the read address is the last data word corresponding to the read address presented to the structure in a write operation.

8. The structure of claim 1, wherein the predetermined number of clock cycles is one.

9. The structure of claim 1, wherein the predetermined number of clock cycles is two.

10. The structure of claim 1, wherein the predetermined number of clock cycles is greater than two.

11. A memory structure, comprising:

at least two address registers coupled in series, each of the at least two address registers including an enable terminal such that the at least two address registers store an address presented to their input terminals on a rising edge of a clock signal;

at least two data registers coupled in series, each of the at least two data registers storing a data word presented to their input terminals on the rising edge of the clock signal;

a memory array;

a logic circuit coupled to the at least two address registers, the at least two data registers, and the memory array, the logic circuit coupled to control presentation of addresses stored in the at least two address registers and data words stored in the at least two data registers to the memory array; and

wherein, in a write operation, the logic circuit controls the at least two address registers and the at least two data registers such that write address is stored in the at least two address registers in a first write clock cycle and a write data word corresponding to the write address is stored in the at least two data registers in a second write clock cycle following the first write clock cycle by a predetermined number of clock cycles, and

wherein, in a read operation, the logic circuit controls the at least two address registers and the at least two data registers such that a read address is presented in a first read clock cycle and a read data word corresponding to the read address is presented to an output terminal in a second read clock cycle following the first read clock cycle by the predetermined number of clock cycles.

12. The structure of claim 11, wherein the predetermined number of clock cycles is one.

13. The structure of claim 11, wherein the predetermined number of clock cycles is two.

14. The structure of claim 11, wherein the predetermined number of clock cycles is greater than two.

15. The structure of claim 11, wherein during the write operation an address and corresponding data word are presented to the memory array.

16. The structure of claim 11, wherein during the read operation if the read address matches an address stored in the at least one address register, the read data word is output from the at least one data register.

17. The structure of claim 11, wherein a second write operation may occur in a clock cycle immediately following the first clock cycle.

18. The structure of claim 11, wherein the write operation may occur in a clock cycle immediately following the clock cycle when the read operation is presented.

19. The structure of claim 11, wherein the read operation may occur in a clock cycle immediately following the first clock cycle.

20. The structure of claim 11, wherein a second read operation may occur in a clock cycle immediately following the clock cycle when the read is presented.