Rapid defect analysis by placement of tester fail data

• US 6,785,413 B1
• Filed: 08/24/1999
• Issued: 08/31/2004
• Est. Priority Date: 08/24/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huisman, Leendert M., Quandt, Kevin C., Barcomb, Kevin J.
• Primary Examiner(s): Patel, Jayanti K.
• Assistant Examiner(s): CHAWAN, SHEELA C
• Application Number:
  US09/379,772
• Time in Patent Office: 1,834 Days
• Field of Search: 382/145, 382/147, 382/149, 714/33, 714/40, 714/42, 714/54, 714/700, 714/728, 714/732, 714/738, 714/733, 714/736, 438/10, 438/17, 348/87, 324/73.1, 703/13, 703/15, 716/4, 716/6
• US Class Current: 382/149
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A structure and method for identifying a physical location of a defect in a logic circuit based on a physical location of a logic latch having failing data. The logic circuit includes a plurality of logic latches, each having a predetermined physical location within the logic circuit. The logic latches are connected to devices adjacent the logic latches, such that the failing data in the logic latch indicates a failure of a device adjacent the logic latches.

Claims

1. A method of locating a physical location of a defect in an integrated circuit chip comprising:

identifying exact physical locations of logic latches within said integrated circuit chip;

supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce failing data in said logic latches; and

identifying said physical location of said defect in said integrated circuit chip based on physical locations of said logic latches having failing data.

2. The method of claim 1, wherein said logic latch are connected to devices adjacent said logic latches, such that said failing data in said logic latch indicates a failure of at least one device adjacent said logic latch.

3. The method of claim 1, further comprising displaying a map of said physical locations of said logic latch having failing data.

4. The method of claim 1, further comprising determining an area adjacent to at least one of logic latch having failing data.

5. The method of claim 1, further comprising recognizing a pattern of said logic latches having failing data to determine if similar patterns of failing locations occur on other similarly manufactured integrated circuit chips.

6. The method of claim 1, further comprising the step of calculating the physical location of latches from design data before testing, transforming chip based locations of said latches to wafer based locations, looking up the chip based physical location of latches having failing data, and calculating the wafer based location of said latches having failing data.

7. The method of claim 1, further comprising running a scan chain testing procedure to identify said physical locations of said logic latches having failing data.

8. A method of identifying approximate physical locations of defects in an integrated circuit chip, said method comprising:

supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce ailing data in logic latches in response to said test signals;

identifying physical locations of logic lathes that have said failing data; and

identifying approximate locations of defects in said integrated circuit chip as those areas that are adjacent to said logic latches that have said failing data.

9. The method of claim 8, wherein said logic latch are connected to devices physically adjacent said logic latches, such that said failing data in said logic latch indicates a failure of at least one device physically adjacent said logic latch.

10. The method of claim 8, further comprising:

calculating said physical locations of said logic latches from design data before supplying said test signals; and

transforming chip based locations of said defects to wafer based locations.

11. The method of claim 8, further comprising recognizing a pattern of sad logic latches having failing data to determine if similar patterns of failing locations occur on other similarly manufactured integrated circuit chips.

12. The method of claim 8, wherein said process of identifying physical locations of said physical latches is based on predetermined physical layout design coordinates of said latches.

13. The method of claim 8, wherein said process of identifying physical locations of said latches avoids performing a logical-to-physical conversion of data contained within said latches.

14. A method of identifying approximate physical locations of defects in an integrated circuit chip, said method comprising:

supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce failing data in logic latches in response to said test signals;

identifying physical locations of logic latches that have said failing data; and

displaying a map of said physical locations of said logic latch having failing data to graphically identify approximate locations of defects in said integrated circuit chip.

15. The method of claim 14, wherein said logic latch are connected to devices physically adjacent said logic latches, such that said failing data in said logic latch indicates a failure of at least one device physically adjacent said logic latch.

16. The method of claim 14, further comprising calculating said physical locations of said logic latches front design data before supplying said test signals.

17. The method of claim 14, further comprising transforming chip based locations of said defects to wafer based locations.

18. The method of claim 14, further comprising recognizing a pattern of said logic latches having failing data to determine if similar patterns of filing locations occur on other similarly manufactured integrated circuit chips.

19. The method of claim 14, wherein said process of identifying physical locations of said physical latches is based on predetermined physical layout design coordinates of said latches.

20. The method of claim 14, wherein said process of identifying physical locations of said latches avoids performing a logical-to-physical conversion of data contained within said latches.