Synchronous flash memory with non-volatile mode register

• US 6,785,764 B1
• Filed: 05/11/2000
• Issued: 08/31/2004
• Est. Priority Date: 05/11/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/569,218
• Time in Patent Office: 1,573 Days
• Field of Search: 711/103, 711/167, 711/168, 711/169, 711/162, 711/119, 711/113, 713/200, 713/300, 713/1, 713/2, 710/10, 710/16
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.

Claims

1. A synchronous non-volatile memory comprising:

an array of non-volatile memory cells;

control circuitry;

a non-volatile mode register having a plurality of bit locations to store mode data;

a volatile mode register coupled to the non-volatile mode register to receive a copy of the mode data, the control circuitry is coupled to the volatile mode register such that the control circuitry establishes operating settings in response to the mode data stored in the volatile mode register.

2. The synchronous non-volatile memory of claim 1 wherein the operating settings comprise a standard length of burst read operations that can be performed by the control circuitry in response to a burst read operation command.

3. The synchronous non-volatile memory of claim 1 wherein the operating settings comprise an address-sequencing scheme during burst operations.

4. The synchronous non-volatile memory of claim 1, wherein the operating settings comprise a clock latency value for data read operations.

5. The synchronous non-volatile memory of claim 1 wherein the mode data stored in either the volatile mode register or the non-volatile mode register can be edited.

6. A processing system comprising:

a processor; and

a synchronous non-volatile memory coupled to the processor and comprising,

an array of non-volatile memory cells,

control circuitry,

a non-volatile mode register having a plurality of bit locations to store mode data and wherein the control circuitry establishes operating settings in response to the mode data, and

a volatile mode register coupled to the non-volatile mode register to receive a copy of the mode data;

wherein the processor provides commands to the synchronous non-volatile memory to initiate a memory read operation, and the synchronous non-volatile memory provides output data to the processor and the operating settings.

7. The processing system of claim 6 wherein the operating settings control a length of burst read operations, an address-sequencing scheme to be used during burst operations, or a clock latency value for data read operations.

8. The processing system of claim 7 wherein the synchronous non-volatile memory comprises a plurality of address connection coupled to the processor, wherein the processor can edit the mode data stored in either the volatile or non-volatile mode register using the address connections.

9. A method of operating a synchronous non-volatile memory device comprising:

programming a non-volatile mode register with mode data;

providing power to the memory device;

copying the mode data from the non-volatile to a volatile mode register;

initiating a data access operation;

reading the mode data from the volatile mode register; and

controlling the data access operation in response to the mode data.

10. The method of claim 9 further comprises editing the mode data stored in the volatile mode register.

11. A method of reading data from a non-volatile memory device comprising:

programming a non-volatile mode register with mode data;

copying the mode data from the non-volatile to a volatile mode register;

reading mode data from the volatile mode register;

adjusting a clock latency value to X in response to the mode data;

receiving a memory read command in synchronization with a first clock signal transition; and

outputting memory data read from non-volatile memory cells on data communication connections in synchronization with a second clock signal transition, wherein the second clock signal transition follows the first clock signal transition.

12. The method of claim 11 wherein X is one, two or three.

14. The method of claim 12 wherein X is selected from the group comprising 2, 4, 8 and 256.

13. A method of reading data from a non-volatile memory device comprising:

programming a non-volatile mode register with mode data;

copying the mode data from the non-volatile to a volatile mode register;

reading mode data from the volatile mode register;

adjusting a burst length to a value of X in response to the mode data;

receiving a memory burst read command;

receiving a first memory address; and

outputting memory data read from non-volatile memory cells communication connections starting at the first memory address and sequentially outputting memory data read from X−

1 additional memory address locations.

15. A method of reading data from a non-volatile memory device comprising:

programming a non-volatile mode register with mode data;

copying the mode data from the non-volatile to a volatile mode register;

reading mode data from the volatile mode register;

adjusting an addressing sequence in response to the mode data;

receiving a memory burst read command;

receiving a first memory address; and

reading data from a memory location having the first memory address; and

generating a second memory address based upon the address sequence;

reading data from the second memory address.

16. The method of claim 15 wherein the address sequence is either sequential or an interleaved sequence.