Read/write alignment scheme for port reduction of multi-port SRAM cells

• US 6,785,781 B2
• Filed: 04/03/2001
• Issued: 08/31/2004
• Est. Priority Date: 04/20/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wendel, Dieter, Leenstra, Jens, Pille, Juergen, Sautter, Rolf
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Song, Jasmine
• Application Number:
  US09/825,072
• Publication Number:
  US 20010034817A1
• Time in Patent Office: 1,246 Days
• Field of Search: 711/168, 711/149, 711/150, 711/169, 365/230.02, 365/230.05, 365/189.02, 365/189.04
• US Class Current: 711/149
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

Claims

1. A method for efficiently accessing multi-port cell array circuitry, each cell of said array being usable by an at least n-times multiple concurrent access, the method comprising:

controlling said multiple concurrent access in a plurality of groups, a group being defined by a plurality of array accesses directed to a the same cell port, wherein one array access of the plurality of array accesses is directed to the same cell port at a single time, and wherein the same cell port is unique to the group being defined.

2. The method according to claim 1, further comprising:

aligning the accesses from a number of n1 write requestors to n1 different write ports, followed by writing concurrently to said write ports;

reading from the array by concurrently reading from n2 read ports; and

aligning the read result according to the n2 read requestor.

3. The method according to claim 1 used for operating an instruction window buffer memory for processing out-of-order instructions.

4. The method according to claim 1 used for operating a buffer memory in which the operation of a queue is managed.

5. A hardware circuit comprising a multi-port array storage device usable by a n1-times concurrent write access, and a n2-times concurrent read access, said storage device being characterized by comprising:

a plurality of n1 write ports, and n2 read ports;

a controlling means being feedable via a control line with a respective control information specifying which cells are intended to be accessed and arranged for selecting respective word select lines;

a write alignment means comprising at least n1 different switching schemata each connecting between one of the respective data input lines and a respective one of said n1 write ports, and said alignment unit being connectable and controllable by the controlling means for properly selecting a respective data line for each of said data lines; and

a read alignment means having a control input and comprising at least n2 different switching schemes for selecting n2 different array entries according to said control input.

6. The hardware circuit of claim 5 in which n1 equals n2.

7. The hardware circuit of claim 5 comprising a multiport array or a multiport register.

8. A sub-unit for use in microprocessor devices having at least one hardware circuit according to claim 5.

9. A microprocessor device having at least one sub-unit according to claim 8.

10. A computer system having a microprocessor device according to claim 9.

11. A computer system having a microprocessor device, said microprocessor device having one or more subunits, at least one subunit of said one or more subunits having one or more hardware circuits, at least one hardware circuit of said one or more hardware circuits comprising a multi-port array storage device usable by a n1-times concurrent write access, and a n2-times concurrent read access, said storage device comprising:

a plurality of n1 write ports, and n2 read ports;

a controlling means being feedable via a control line with a respective control information specifying which cells are intended to be accessed and arranged for selecting respective word select lines;

a write alignment means comprising at least n1 different switching schemata each connecting between one of the respective data input lines and a respective one of said n1 write ports, and said alignment unit being connectable and controllable by said controlling means for properly selecting a respective data line for each of said data lines; and

a read alignment means having a control input and comprising at least n2 different switching schemes for selecting n2 different array entries according to said control input.

12. The computer system of claim 11, wherein the at least one hardware circuit comprises a multiport array or a multiport register.

13. The computer system of claim 11, wherein n1 equals n2.