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Read/write alignment scheme for port reduction of multi-port SRAM cells

  • US 6,785,781 B2
  • Filed: 04/03/2001
  • Issued: 08/31/2004
  • Est. Priority Date: 04/20/2000
  • Status: Expired due to Fees
First Claim
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1. A method for efficiently accessing multi-port cell array circuitry, each cell of said array being usable by an at least n-times multiple concurrent access, the method comprising:

  • controlling said multiple concurrent access in a plurality of groups, a group being defined by a plurality of array accesses directed to a the same cell port, wherein one array access of the plurality of array accesses is directed to the same cell port at a single time, and wherein the same cell port is unique to the group being defined.

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