Internal self-test circuit for a memory array

• US 6,785,856 B1
• Filed: 12/07/2000
• Issued: 08/31/2004
• Est. Priority Date: 12/07/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Parker, Allan, Skrovan, Joseph
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/732,616
• Time in Patent Office: 1,363 Days
• Field of Search: 714/718-720, 714/728, 714/733-734, 714/738, 714/739, 714/753, 365/200, 324/73.1
• US Class Current: 714/734
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

Claims

1. A method of self-testing a memory device comprising:

testing an entire memory array via an internal self-test including;

accessing the memory array using a wide self-test data path;

clocking the access of the memory array using an internal clock rate; and

read error checking and correcting;

detecting an error; and

generating an error indicator as a function of the detecting the error; and

wherein testing the entire memory array and generating the error indicator are initiated after a threshold number of accesses to the memory array have occurred and are performed autonomously once initiated.

2. The method of claim 1, further comprising generating a cycle count representing a number of times testing the entire memory array is performed.

3. The method of claim 1, further comprising providing an external indication of an end of the testing.

4. The method of claim 1, wherein testing the entire memory array and generating the error indicator is initiated after a threshold number of read accesses to the memory array have occurred.

5. The method of claim 1, wherein testing the entire memory array and generating the error indicator is initiated after the memory array is powered on.

6. The method of claim 1, wherein testing the entire memory array and generating the error indicator is initiated after a memory reset is received.

7. The method of claim 1, wherein the memory array is comprises a plurality of memory pages and each memory page is dividable into a plurality of groups, and wherein testing the entire memory array further comprises testing the memory on a group-by-group basis.

8. The method of claim 7, wherein the testing the entire memory array is performed on a group-by-group bases with a pseudorandom pattern.

9. The method of claim 1, wherein testing the entire memory array further comprises performing read and write operations on each memory cell in the memory array.

10. The method of claim 1, wherein testing the entire memory array further comprises performing read operations on each memory cell in the memory array.

11. The method of claim 10, wherein the memory array comprises an array of flash memory cells.

12. The method of claim 1, wherein testing the entire memory array is terminated when an error is detected.

13. The method of claim 1, wherein testing the entire memory array further comprises omitting a memory cell that is known to be defective.

14. The method of claim 1, wherein testing the entire memory array occurs when memory cells in the memory array contain data and the data is unchanged after the testing.

15. The method of claim 1, wherein the wide self-test data path further comprises a double-wide data path.

16. A memory device comprising:

a memory array;

a self-tester including;

a self-test circuit that performs a test on each memory cell in the memory array and providing a result of the test;

an internal clock that controls a rate of the test, wherein a first clock rate of the internal clock is higher than a second clock rate that is used for external reads of the memory array; and

a wide self-test data path coupling the self-test circuit to the memory array.

17. The memory device of claim 16, wherein the self-tester autonomously tests each memory cell of the memory array.

18. The memory device of claim 17, wherein the self-tester tests the memory cells with a write-read test.

19. The memory device of claim 16, wherein the self-tester tests each memory cell of the memory array sequentially.

20. The memory device of claim 19, wherein the self-tester tests a group of memory cells of the memory array at a time.

21. The memory device of claim 19, wherein the self-tester terminates the test if an error is detected.

22. The memory device of claim 19, wherein the self-tester omits a memory cell that is defective.

23. The memory device of claim 19, wherein the self-tester tests the memory cells when the memory cells contain data and the data is unchanged after the test.

24. The memory device of claim 23, wherein the wide self-test data path comprises a double-wide data path.

25. The memory device of claim 24, wherein the self-tester disables external access to the memory array during tests.

26. The memory device of claim 25, wherein the self-test circuit tests the memory array after a threshold number of accesses to the memory cells of the memory array.

27. The memory device of claim 25, wherein the self-test circuit tests the memory array after a threshold period of time has passed.

28. The memory device of claim 25, wherein a result of the test is stored in a status register.

29. The memory device of claim 25, wherein the self-tester stops the test when an interrupt line is toggled.

30. The memory device of claim 23, wherein the self-test circuit tests the memory array after the memory device is powered on.

31. The memory device of claim 16, wherein the self-tester further comprises an error checking and correcting circuit coupled to the memory array and the self-test circuit by the wide self-test data path that corrects a detected error.

32. A method of self-testing a memory device comprising:

testing an entire memory array via an internal self-test, including;

accessing the memory array using a double-wide data path;

clocking the access of the memory array using an internal clock rate; and

read error checking and correcting;

detecting an error; and

generating an error indicator as a function of the detecting the error; and

wherein testing the entire memory array and generating the error indicator are performed autonomously once initiated.

33. The method of claim 32, further comprising generating a cycle count representing a number of times testing the entire memory array is performed.

34. The method of claim 32, further comprising providing an external indication of an end of the testing.

35. The method of claim 32, wherein testing the entire memory array and generating the error indicator is initiated after a threshold number of read accesses to the memory array have occurred.

36. The method of claim 32, wherein testing the entire memory array and generating the error indicator is initiated after the memory array is powered on.

37. The method of claim 32, wherein testing the entire memory array and generating the error indicator is initiated after a memory reset is received.

38. The method of claim 32, wherein the memory array is comprises a plurality of memory pages and each memory page is dividable into a plurality of groups, and wherein testing the entire memory array further comprises testing the memory on a group-by-group basis.

39. The method of claim 38, wherein the testing the entire memory array is performed on a group-by-group bases with a pseudorandom pattern.

40. The method of claim 32, wherein testing the entire memory array further comprises performing read and write operations on each memory cell in the memory array.

41. The method of claim 32, wherein testing the entire memory array further comprises performing read operations on each memory cell in the memory array.

42. The method of claim 41, wherein the memory array comprises an array of flash memory cells.

43. The method of claim 32, wherein testing the entire memory array is terminated when an error is detected.

44. The method of claim 32, wherein testing the entire memory array further comprises omitting a memory cell that is known to be defective.

45. The method of claim 32, wherein testing the entire memory array occurs when memory cells in the memory array contain data and the data is unchanged after the testing.