Fabrication method of semiconductor integrated circuit device

• US 6,787,446 B2
• Filed: 07/03/2002
• Issued: 09/07/2004
• Est. Priority Date: 08/07/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Enomoto, Hiroyuki, Tago, Kazutami, Maekawa, Atsushi
• Primary Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US10/188,001
• Publication Number:
  US 20030032284A1
• Time in Patent Office: 797 Days
• Field of Search: 438/623, 438/624, 438/634, 438/637, 438/638, 438/687
• US Class Current: 438/623
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76832 Multiple layers

Abstract

The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched. When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF₆ and NH₃ is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves.

Claims

1. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a first interconnection made of a first conductive film containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the first interconnection;

(c) forming a first interlayer insulating film over the first insulating film and subsequently dry-etching a portion of the first interlayer insulating film to make a portion of the first insulating film exposed;

(d) using a first etching gas to dry-etch the first insulating film exposed in the step (c), to form a first interconnection groove wherein the surface of the first interconnection is exposed to its bottom;

(e) forming a second interconnection made of a conductive film containing copper as a main component inside the first interconnection groove;

(f) forming a second insulating film containing silicon carbide or silicon carbonitride as a main component over the second interconnection;

(g) forming a second interlayer insulating film over the second insulating film and subsequently dry-etching a portion of the second interlayer insulating film to make a portion of the second insulating film exposed;

(h) using a second etching gas to dry-etch the second insulating film exposed in the step (g), to form a second interconnection groove wherein the surface of the second interconnection is exposed to its bottom; and

(i) forming a third interconnection made of a conductive film containing copper as a main component inside the second interconnection groove,

wherein one of the first and second etching gases is a mixed gas of a third etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂, ClF₃ and CF₄ and a fourth etching gas comprising at least one selected from the group made of NH₃, H₂H₄, and a mixed gas of N₂ and H₂;

wherein the other thereof is a mixed gas of at least one of CHF₃ and CF₄, and N₂; and

wherein both of the first and second etching gases have a quality of substantially avoiding oxidizing the surface of the interconnection made of a conductive film containing copper.

2. The process according to claim 1, wherein the one of the first and second etching gases is a mixed gas of SF₆ and NH₃ and the other is a mixed gas of CHF₃ and N₂.

3. The process according to claim 1, wherein the first interlayer insulating film is an organic insulating film having a smaller dielectric constant than silicon oxide, the first etching gas is a mixed gas of CHF₃ and N₂, and when the second interlayer insulating film is an insulating film containing a siloxane-based insulating material as a main component, the second etching gas is a mixed gas of SF₆ and NH₃.

4. The process according to claim 3, wherein the first interlayer film is a coating film containing an aromatic polymer as a main component.

5. The process according to claim 3, wherein the second interlayer insulating film is an insulating film containing SiOF as a main component.

6. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide or silicon carbonitride as a main component over the conductive layer;

(c) forming a second insulating film made of an organic insulating film having a smaller dielectric constant than silicon oxide over the first insulating film;

(d) using a gas containing nitrogen and hydrogen to dry-etch a portion of the second insulating film, thereby making a portion of the first insulating film exposed; and

(e) using a mixed gas of SF₆ and NH₃, which does not contain oxygen, to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.

7. A process of fabricating a semiconductor integrated circuit device comprising the steps of:

(a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate;

(b) forming a first insulating film containing silicon carbide, silicon carbonitride or silicon carboxide as a main component over the conductive layer;

(c) forming a second insulating film made of an organic insulating film having a smaller dielectric constant than silicon oxide over the first insulating film;

(d) using a gas containing nitrogen and hydrogen to dry-etch a portion of the second insulating film, thereby making a portion of the first insulating film exposed; and

(e) using a mixed gas of a first etching gas comprising at least one selected from the group made of SF₆, HCl, HBr, Cl₂, ClF₃ and CF₄ and a second etching gas comprising at least one selected from the group made of NH₃, N₂H₄, and a mixed gas of N₂ and H₂ to dry-etch a portion of the first insulating film, wherein the mixed gas of the first etching gas and the second etching gas has a quality of substantially avoiding oxidizing the surface of the conductive layer containing copper, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom.