Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process
First Claim
1. A method for reducing electrical discharges within semiconductor wafers comprising the steps of:
- providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects;
exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and
, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
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Abstract
A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process water; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
11 Citations
20 Claims
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1. A method for reducing electrical discharges within semiconductor wafers comprising the steps of:
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providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects;
exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and
,limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18, 19, 20)
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14. A method for reducing time dependent dielectric arcing (TDDA) within a semiconductor process wafer comprising the steps of:
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exposing a photoresist layer overlying the semiconductor process wafer to a source of activating radiation;
limiting the semiconductor process wafer exposure to visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer. - View Dependent Claims (15, 16, 17)
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Specification