Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process

• US 6,787,484 B2
• Filed: 12/17/2002
• Issued: 09/07/2004
• Est. Priority Date: 12/17/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yao, Chih-Hsiang, Lu, Yun-Cheng
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US10/322,412
• Publication Number:
  US 20040115943A1
• Time in Patent Office: 630 Days
• Field of Search: 438/706, 438/795, 438/730, 438/727, 438/692, 438/710, 438/514, 438/519, 438/308, 438/725
• US Class Current: 438/795
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers

Abstract

A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process water; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.

Claims

1. A method for reducing electrical discharges within semiconductor wafers comprising the steps of:

providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects;

exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and

,

limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.

2. The method of claim 1, wherein the semiconductor process includes at least one of a lithographic patterning process, a plasma assisted process, and a chemical mechanical polishing process.

3. The method of claim 2, wherein the semiconductor process comprises a photolithographic process comprising exposure to radiation having wavelengths of less than about 400 nm.

4. The method of claim 3, wherein the semiconductor process comprises a photolithographic process comprising exposure to radiation having wavelengths of less than about 250 nm.

5. The method of claim 3, whereby the electrical charge imbalances accumulates upon exposure of a photoresist layer overlying the at least one dielectric insulating layer.

6. The method of claim 1, wherein the visible light is limited to wavelengths of greater than about 560 nm.

7. The method of claim 1, wherein the visible light is limited to wavelengths of between about 560 nm and about 620 nm.

8. The method of claim 1, wherein the visible light is limited to wavelengths of between about 590 nm and about 600 nm.

9. The method of claim 1, wherein the step of limiting comprises at least one of transporting and storing the semiconductor process wafer.

10. The method of claim 1, wherein the step of limiting comprises providing a light filtering means between a visible light source and the semiconductor process wafer.

11. The method of claim 1, wherein the step of limiting comprises providing a light source limited to producing wavelengths greater than the predetermined lower limit.

12. The method of claim 1, wherein the at least one dielectric layer comprises carbon doped oxide and the metal interconnects comprise copper.

13. The method of claim 1, wherein the at least one dielectric layer comprises features having a critical dimension of less than about 0.25 microns.

18. The method of claim 1, wherein the visible light is limited to wavelength of between about 560 nm and about 620 nm.

19. The method of claim 1, wherein the visible light is limited to wavelength of between about 590 nm and about 600 nm.

20. The method claim 1, wherein the step of limiting comprising providing means least one of a light filtering means or a light producing means and the period of time comprises at least one of transporting and storing the semiconductor process wafer.

14. A method for reducing time dependent dielectric arcing (TDDA) within a semiconductor process wafer comprising the steps of:

exposing a photoresist layer overlying the semiconductor process wafer to a source of activating radiation;

limiting the semiconductor process wafer exposure to visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.

15. The method of claim 14, wherein the activating radiation comprises wavelengths of less than about 400 nm.

16. The method of claim 15, wherein the activating radiation comprises wavelengths of less than about 250 nm.

17. The method of claim 15, wherein the visible light is limited to wavelengths of greater than about 560 nm.