Logic apparatus and logic circuit

• US 6,787,795 B2
• Filed: 11/23/2001
• Issued: 09/07/2004
• Est. Priority Date: 11/24/2000
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Koga, Junji, Ohba, Ryuji, Uchida, Ken
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/990,362
• Publication Number:
  US 20020096740A1
• Time in Patent Office: 1,019 Days
• Field of Search: 257/9, 257/30, 257/39, 257/532, 257/536, 257/553
• US Class Current: 257/30
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/7888 Transistors programmable by two single electrons
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H10N 99/05 Quantum devices, e.g. quantum interference devices, metal single electron transistors

Abstract

A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.

Claims

1. A logic apparatus comprising:

a semiconductor substrate;

a first single-electron device comprising,

a first conductive island insulatively disposed over the semiconductor substrate,

at least two first tunnel barriers insulatively disposed over the semiconductor substrate, the first conductive island being interposed between the first tunnel barriers,

first and second electrodes insulatively disposed over the semiconductor substrate, the first conductive island being coupled with the first and second electrodes through the first tunnel barriers, respectively, and

a first charge storage region insulatively disposed over the first conductive island;

a second single-electron device comprising,

a second conductive island insulatively disposed over the semiconductor substrate,

at least two second tunnel barriers insulatively disposed over the semiconductor substrate, the second conductive island being interposed between the second tunnel barriers,

third and fourth electrodes insulatively disposed over the semiconductor substrate, the second conductive island being coupled with the third and fourth electrodes through the second tunnel barriers, respectively, and

a second charge storage region insulatively disposed over the second conductive island; and

a connection between the third electrode of the second single-electron device and the first electrode of the first single-electron device,

wherein, for each of the first and second single-electron devices, a Coulomb oscillation in a state that charges are accumulated in the charge storage region is shifted by a half-period from the Coulomb oscillation in a state that no charge is accumulated therein.

2. A logic apparatus according to claim 1, further comprising an output amplifier connected to the first electrode of the first single-electron device and the third electrode of the second single-electron device.

3. A logic apparatus according to claim 1, wherein the first and second single-electron devices include fifth and sixth electrodes insulatively disposed over the first and second charge storage regions, respectively, logic signals are input to the fifth and sixth electrodes of the first and second single-electron devices, and a logic operation result is output from the first and third electrodes.

4. A logic apparatus according to claim 3, wherein the first electrode and the third electrode are formed of a common electrode region.

5. A logic apparatus according to claim 1, wherein the first and second single-electron devices include fifth and sixth electrodes insulatively disposed over the first and second charge storage regions, respectively, logic signals are input to the fifth and the sixth electrode of the first and the second single-electron device, and a logic operation result is output from the second electrode of the first single-electron device.

6. A logic apparatus according to claim 5, wherein the first electrode and the third electrode are formed of a common electrode region.

7. A logic apparatus according to claim 1, wherein each of the first and second single-electron devices has a logic inversion relation between a state that charges are accumulated in the charge storage region and a state that no charge is accumulated therein.

8. A logic apparatus according to claim 1, wherein each of the first and second single-electron devices further comprises an element configured to inject charges to the charge storage region or extract charges therefrom.

9. A logic apparatus according to claim 1, wherein each of the first and second single-electron devices further comprises an element configured to generate a potential difference between the conductive island and the charge storage region, in order to inject charges to the charge storage region or extract charges therefrom.

10. A logic apparatus according to claim 1, wherein, for each of the first and second single-electron devices, a size and materials of the conductive island are selectively set to shift the Coulomb oscillation by the half-period between the state that charges are accumulated in the charge storage region and the state that no charge is accumulated therein.

11.A logic apparatus comprising:

a semiconductor substrate;

a first single-electron device comprising,

a first conductive island insulatively disposed over the semiconductor substrate,

at least two first tunnel barriers insulatively disposed over the semiconductor substrate, the first conductive island being interposed between the first tunnel barriers,

first and second electrodes insulatively disposed over the semiconductor substrate, the first conductive island being coupled with the first and second electrodes through the first tunnel barriers, respectively, and

a first charge storage region insulatively disposed over the first conductive island;

a second single-electron device comprising,

a second conductive island insulatively disposed over the semiconductor substrate,

at least two second tunnel barriers insulatively disposed over the semiconductor substrate, the second conductive island being interposed between the second tunnel barriers,

third and fourth electrodes insulatively disposed over the semiconductor substrate, the second conductive island being coupled with the third and fourth electrodes through the second tunnel barriers, respectively, and

a second charge storage region insulatively disposed over the second conductive island; and

a connection between the third electrode of the second single-electron device and the first electrode of the first single-electron device;

a resistor between a node of the first electrode of the first single-electron device, the third electrode of the second single-electron device, and a voltage source; and

at least one ground terminal connected to the second electrode of the first single-electron device and the fourth electrode of the second single-electron device.

11. A logic apparatus according to claim 1, further comprising a plurality of single-electron device pairs each including the first and second single-electron devices connected in parallel or serial.

12. A logic apparatus according to claim 1, further comprising a plurality of single-electron device pairs each including the first and second single-electron devices connected in parallel and serial.

13. A logic circuit comprising:

a first logic circuit using a single-electron device having an oscillation according to a voltage, a capacitor configured to selectively store charges, a first terminal, a second terminal, and a third terminal;

a second logic circuit using a single-electron device having an oscillation according to a voltage, a capacitor configured to selectively store charges, a first terminal connected to the first terminal of the first logic circuit, a second terminal, and a third terminal;

a resistor connected to a node of the first terminals of the first and second logic circuits and a voltage source;

a ground terminal connected to the second terminals of the first and second logic circuits; and

logic signal input terminals, connected to the third terminals of the first and second logic circuit, inputted with logic signals.

14. A logic circuit according to claim 14, further comprising an output amplifier connected to the node of the first terminals of the first and second logic circuit.

15. A logic circuit according to claim 14, wherein a logic operation result is output from the first terminals of the first and second logic circuits.

16. A logic circuit according to claim 14, wherein a logic operation result is output from the second terminal of the first logic circuit.

17. A logic circuit according to claim 14, wherein each of the first and second logic circuits has a logic inversion relation between a state that charges are accumulated in the capacitor and a state that no charge is accumulated therein.

18. A logic circuit according to claim 14, which includes further comprising a circuit configured to inject charges to the capacitor or extract charges therefrom.

19. A logic circuit according to claim 14, further comprising a plurality of logic circuit pairs each including the first and second logic circuits connected in parallel or serial.

20. A logic circuit according to claim 14, further comprising a plurality of logic circuit pairs each including the first and second logic circuits connected in parallel and serial.

21. A logic apparatus comprising:

a semiconductor substrate;

a first single-electron device comprising,

a first conductive island insulatively disposed over the semiconductor substrate,

at least two first tunnel barriers insulatively disposed over the semiconductor substrate, the first conductive island being interposed between the first tunnel barriers,

first and second electrodes insulatively disposed over the semiconductor substrate, the first conductive island being coupled with the first and second electrodes through the first tunnel barriers, respectively, and

a first means for storing charges to vary an energy state of the first conductive island;

a second single-electron device comprising,

a second conductive island insulatively disposed over the semiconductor substrate,

at least two second tunnel barriers insulatively disposed over the semiconductor substrate, the second conductive island being interposed between the second tunnel barriers,

third and fourth electrodes insulatively disposed over the semiconductor substrate, the second conductive island being coupled with the third and fourth electrodes through the second tunnel barriers, respectively, and

a second means for storing charges to vary an energy state of the second conductive island; and

a connection between the third electrode of the second-single electron device and the first electrode of the first single-electron device,

wherein, for each of the first and second single-electron devices, a Coulomb oscillation in a state that charges are accumulated in the means for storing charges is shifted by a half-period from the Coulomb oscillation in a state that no charge is accumulated therein.

22. A logic apparatus according to claim 22, wherein the first and second single-electron devices include fifth and sixth electrodes insulatively disposed over the first and second means for storing charges, respectively, logic signals are input to the fifth and sixth electrodes of the first and second single-electron devices, and a logic operation result is output from the first and third electrodes.

23. A logic apparatus according to claim 22, wherein the first and second single-electron devices include fifth and sixth electrodes insulatively disposed over the first and second means for storing charges, respectively, logic signals are input to the fifth and sixth electrode of the first and second single-electron device, and a logic operation result is output from the second electrode of the first single-electron device.

24. A logic apparatus according to claim 22, wherein each of the first and second single-electron devices has a logic inversion relation between a state that charges are accumulated in the means for storing charges and a state that no charge is accumulated therein.

25. A logic apparatus comprising:

a semiconductor substrate;

a first single-electron device comprising,

a first conductive island insulatively disposed over the semiconductor substrate,

at least two first tunnel barriers insulatively disposed over the semiconductor substrate, the first conductive island being interposed between the first tunnel barriers,

first and second electrodes insulatively disposed over the semiconductor substrate, the first conductive island being coupled with the first and second electrodes through the first tunnel barriers, respectively, and

a first means for storing charges to vary an energy state of the first conductive island;

a second single-electron device comprising,

a second conductive island insulatively disposed over the semiconductor substrate,

at least two second tunnel barriers insulatively disposed over the semiconductor substrate, the second conductive island being interposed between the second tunnel barriers,

third and fourth electrodes insulatively disposed over the semiconductor substrate, the second conductive island being coupled with the third and fourth electrodes through the second tunnel barriers, respectively, and

a second means for storing charges to vary an energy state of the second conductive island;

a connection between the third electrode of the second-single electron device and the first electrode of the first single-electron device;

a resistor between a node of the first electrode of the first single-electron device, the third electrode of the second single-electron device, and a voltage source; and

at least one ground terminal connected to the second electrode of the first single-electron device and the fourth electrode of the second single-electron device.