Wafer-level package with silicon gasket

• US 6,787,897 B2
• Filed: 12/20/2001
• Issued: 09/07/2004
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Figueredo, Domingo A, Mattos, Ann, Gan, Qing, Geefay, Frank S
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): CRUZ, LOURDES C
• Application Number:
  US10/028,058
• Publication Number:
  US 20030116825A1
• Time in Patent Office: 992 Days
• Field of Search: 257/619, 257/704, 257/705, 257/784, 257/787, 174/52-- 5, 361/762-764, 361/785, 438/107, 438/125, 438/700, 438/455, 438/456
• US Class Current: 257/704
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.

Claims

1. A wafer-level package, comprising:

a first semiconductor wafer having an elevated portion and an etched lower surface, wherein the elevated portion has a flat surface original to the semiconductor wafer amid surrounds an area of the etched lower surface;

a device fabricated on the first semiconductor wafer;

a second semiconductor wafer;

a pad on the second semiconductor wafer, substantially matching the gasket elevated portion; and

bonding material joining the elevated portion and the pad to enclose the device within a hermetically sealed environment between the first and second semiconductor wafers.

2. The wafer-level package of claim 1 wherein the first wafer is formed of silicon.

3. The wafer-level package of claim 2 wherein the elevated portion is no more than 20 μ

m wide.

4. The wafer-level package of claim 3 wherein the elevated portion is no more than 10 μ

m wide.

5. The wafer-level package of claim 3 wherein the bonding material includes conductive bonding material.

6. The wafer-level package of claim 5 wherein the conductive bonding material is a metal selected from the group consisting of gold, gold-tin, tin-lead, and palladium-tin.

7. The wafer-level package of claim 3 wherein the bonding material includes non-conductive bonding material.

8. The wafer-level package of claim 7 wherein the non-conductive bonding material is a material selected from the group consisting of polyimide, B-staged bisbenzocyclobutene (BCB), and glass.

9. A wafer-level package, comprising:

a first semiconductor wafer having an elevated portion and an etched lower surface, wherein the elevated portion has a flat surface original to the semiconductor wafer and surrounds an area of the etched lower surface;

a device fabricated on the first semiconductor wafer;

a second semiconductor wafer;

bonding material joining the elevated portion and the second semiconductor wafer to enclose the device within a hermetically sealed environment between the first and second semiconductor wafers.

10. The wafer-level package of claim 9, wherein the elevated portion is less than 20 μ

m wide.

11. The wafer-level package of claim 10, wherein the elevated portion is less than 10 μ

m wide.

12. The wafer-level package of claim 10, wherein the bonding material is non-conductive.

13. The wafer-level package of claim 12, wherein the non-conductive bonding material is selected from the group consisting of polyimide, B-staged bisbenzocyclobutene (BOB), and glass.