Serial bus control method and apparatus for a microelectronic power regulation system

• US 6,788,035 B2
• Filed: 06/12/2002
• Issued: 09/07/2004
• Est. Priority Date: 06/12/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Primarion Incorporated (Infineon Technologies AG)
• Inventors: Steffen, Nicholas, Bassett, Keith, Carroll, Robert, Tang, Benjamin, Ostrom, Kenneth, Ng, Tim
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US10/167,911
• Publication Number:
  US 20030090255A1
• Time in Patent Office: 818 Days
• Field of Search: 323/225, 323/226, 323/272, 323/273, 323/276, 323/274, 323/282, 323/288, 323/285, 361/111, 361/18, 361/92, 361/228, 361/189, 361/93.1, 361/93.2, 710/108, 710/109, 363/35, 363/37, 363/38, 363/39, 363/40, 363/41, 363/72, 363/56.02, 363/88, 307/66, 307/83, 307/17, 307/29
• US Class Current: 323/272
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H05K 1/181 associated with surface mounted components

Abstract

A serial bus control method, apparatus, and system for transmitting signals between a master controller and a slave controller associated with a power regulator are disclosed. The serial bus control scheme allows for information to be written to or read from individual regulators or be written to read from all regulators that are coupled to the master controller.

Claims

1. A system for transmitting signals between a master controller and a secondary regulator, the system comprising:

a master controller;

a primary regulator coupled between the master controller and a load to provide low frequency power regulation;

a communication bus coupled to the master controller; and

a secondary regulator, including a serial interface, coupled to the communication bus and the master controller, wherein the secondary regulator is configured to receive information from the master controller and to transmit information to the master controller and to suppress high speed transients.

2. The system of claim 1, wherein the communication bus comprises two transmission lines.

3. The system of claim 2, wherein the communication bus comprises a clock transmission line and a data transmission line.

4. The system of claim 1, further comprising a plurality of secondary regulators coupled to the communication bus.

5. The system of claim 1, wherein the serial interface is configured to receive serial information, transform the serial information to parallel information, process the parallel information, and transmit serial information to the master controller.

6. The system of claim 1, wherein the serial interface comprises a shift register, a register, and control logic.

7. The system of claim 6, wherein the serial interface further includes a bit counter and a plurality of multiplexers.

8. The system of claim 1, wherein the interface is configured to run a built-in test operation.

9. The system of claim 1, wherein the interface is configured to run a status check operation.

10. The system of claim 1, wherein the interface includes a tri-state buffer configured to select one of three possible states of output data.

11. The system of claim 1, wherein the master controller and the secondary regulator are configured to communicate using a digital word having the first four bits dedicated to an address the secondary regulator.

12. The system of claim 1, wherein the master controller and the secondary regulator are configured to communicate using a digital word having two bits dedicated to the mode of operation.

13. The system of claim 1, wherein the master controller and the secondary regulator are configured to communicate using a digital word having ten bits dedicated to slave status.

14. The system of claim 1, wherein the master controller and the secondary regulator are configured to communicate using a digital word having thirty-six bits dedicated to slave data.

15. The system of claim 1, wherein the interface is configured to read information during a rise of a clock signal.

16. The system of claim 1, wherein interface write information transmitted from the master controller to the secondary regulator comprises information selected from the group consisting of:

output enable output enable, threshold adjust, magnitude adjust, output current pulse slope, output current pulse slope, sense amp gain, sense amp threshold, thermal shutdown threshold, charge well trip level, flash out enable, allowed fire count, force comparator on, test mode, di/dt bank duration, charge well sense locale, and output switch state.

17. A method of communicating between a master controller and a secondary regulator, the method comprising the steps of:

providing a master controller;

providing at least one primary controller to provide low frequency power regulation,

providing a plurality of secondary regulators to suppress high speed transients, wherein each regulator comprises a slave controller; and

transmitting digital information between the master controller and the secondary regulator.

18. The method of claim 17, wherein the step of transmitting information comprises providing a digital word having the first four bits dedicated to the address for the secondary regulator.

19. The method of claim 17, wherein the step of transmitting information comprises providing a digital word having two pits dedicated to the mode of operation.

20. The method of claim 17, wherein the step of transmitting information comprises providing a digital word having ten bits dedicated to slave status.

21. The method of claim 17, wherein the step of transmitting information comprises providing a digital word having thirty-six bits dedicated to slave data.

22. The method of claim 17, further comprising the step of reading information transmitted from the master controller during a rise of a clock signal.

23. The method of claim 17, further comprising the step of writing information to a portion of the secondary regulator.

24. The method of claim 23, wherein the step of writing comprises writing information selected from the group consisting of:

output enable output enable, threshold adjust, magnitude adjust, output current pulse slope, output current pulse slope, sense amp gain, sense amp threshold, thermal shutdown threshold, charge well trip level, flash out enable, allowed fire count, force comparator on, test mode, di/dt bank duration, charge well sense locale, and output switch state.

25. A system for transmitting signals between a master controller and a secondary regulator, the system comprising:

a master controller;

a primary regulator coupled between the master controller and a load to provide low frequency power regulation,

a communication bus coupled to the master controller; and

a secondary regulator, including a serial interface, coupled to the communication bus and the master controller to suppress high speed transients,

wherein the master controller and the serial interface communicate using a protocol that supports write, broadcast write, output enable, broadcast output enable, read status, broadcast read status, and read command.