Data processing systems having mismatched impedance components

• US 6,788,073 B2
• Filed: 09/06/2002
• Issued: 09/07/2004
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Wallace, Douglas E., Lash, Steven J., Saputro, Stephanus D.
• Primary Examiner(s): Le, N.
• Assistant Examiner(s): Lair, Donald M.
• Application Number:
  US10/236,807
• Publication Number:
  US 20030038639A1
• Time in Patent Office: 732 Days
• Field of Search: 324/642, 324/534, 324/532, 324/535, 333/33, 439/91, 439/108, 716/4, 716/1
• US Class Current: 324/642
• CPC Class Codes: G01R 31/11 using pulse reflection methods
• CPC Class Codes: G01R 31/2813 Checking the presence, location, orientation or value, e.g. resistance, of components or conductors orientation of the DUT with respect to the test fixture G01R1/06705, G01R31/281
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2203/171 Tuning, e.g. by trimming of printed components or high frequency circuits

Abstract

A data processing system having mismatched impedance components and method of use is disclosed. In one embodiment, the method includes exciting a printed circuit board circuit having mismatched impedance printed circuit board components. Measuring at least one impedance of the circuit with a time domain reflectometer. In response to the measured at least one impedance of the circuit, adjusting at least one printed circuit board circuit element.

Claims

1. A method comprising:

exciting a printed circuit board circuit having mismatched impedance printed circuit board components, the mismatched impedance printed circuit board including at least one Connector Specification component and at least one non-Connector Specification component;

measuring at least one impedance of the circuit with a time domain reflectometer; and

adjusting at least one printed circuit board circuit element, in response to the measured at least one impedance of the circuit.

2. The method of claim 1, wherein said exciting the printed circuit board circuit having the at least one Connector Specification component and the at least one non-Connector Specification component further includes:

exciting the printed circuit board circuit having at least one Connector Specification trace and at least one PCI printed circuit board connector.

3. The method of claim 1, wherein said exciting the printed circuit board circuit having mismatched impedance printed circuit board components further comprises:

exciting the printed circuit board circuit having mismatched impedance printed circuit board components with the time domain reflectometer.

4. A method comprising:

exciting a printed circuit board circuit having mismatched impedance printed circuit board components;

measuring at least one impedance of the circuit with a time domain reflectometer; and

adjusting the at least one printed circuit board circuit element, in response to the measured at least one impedance of the circuit, wherein the adjusting step further includes;

comparing the measured at least one impedance with a defined baseline impedance; and

in response to a determination that a difference between the defined baseline impedance and the measured at least one impedance exceeds a defined tolerance, adjusting the at least one printed circuit board element such that the measured at least one impedance moves toward the defined baseline impedance.

5. The method of claim 4, wherein said adjusting the at least one printed circuit board element such that the measured at least one impedance moves toward the defined baseline impedance further comprises:

adjusting a first printed circuit board element identified as substantially responsible for the measured at least one impedance.

6. The method of claim 5, wherein said adjusting the first printed circuit board element identified as substantially responsible for the measured at least one impedance further includes:

connecting a first end of a shorting strap to a first via and a second end of the shorting strap to a second via.

7. The method of claim 4, wherein said adjusting the printed circuit board element such that the measured at least one impedance moves toward the defined baseline impedance further includes:

adjusting a second printed circuit board element electrically adjacent to the first printed circuit board element identified to be substantially responsible for the measured at least one impedance, such that the second printed circuit board element produces a reflected energy effect opposite that of the first printed circuit board element.

8. The method of claim 7, wherein said adjusting the second printed circuit board element electrically adjacent to the first printed circuit board element identified to be substantially responsible for the measured at least one impedance, such that the second printed circuit board element produces the reflected energy effect opposite that of the first printed circuit board element further includes:

increasing a capacitive effect of the second printed circuit board element if the first printed circuit board element has an inductive effect and increasing the inductive effect of the second printed circuit board element if the first printed circuit board element has the capacitive effect.

9. The method of claim 7, wherein said adjusting the second printed circuit board element electrically adjacent to the first printed circuit board element identified to be substantially responsible for the measured at least one impedance, such that the second printed circuit board element produces the reflected energy effect opposite that of the first printed circuit board element further includes:

introducing the second printed circuit board element substantially adjacent to the first printed circuit board element.

10. A method comprising:

exciting a printed circuit board circuit having mismatched impedance printed circuit board components;

measuring at least one impedance of the circuit with a time domain reflectometer; and

adjusting the at least one printed circuit board circuit element, in response to the measured at least one impedance of the circuit;

wherein adjusting an electrical characteristic of the at least one printed circuit board circuit element if an absolute value of a maximum measured impedance variation above a defined baseline impedance substantially varies from an absolute value of a maximum measured impedance variation below the defined baseline impedance.

11. The method of claim 10, wherein said adjusting the electrical characteristic of the at least one printed circuit board circuit element if the absolute value of the maximum measured impedance variation above the defined baseline impedance substantially varies from the absolute value of the maximum measured impedance variation below the defined baseline impedance further includes:

adjusting the electrical characteristic of the first printed circuit board element such that the absolute value of the maximum measured impedance variation above the defined baseline impedance and the absolute value of the maximum measure impedance variation below the defined baseline impedance become practicably equivalent.

12. A computer system comprising:

one or more printed circuit boards having at least one circuit wherein reside substantially mismatched impedance printed circuit board components;

an impedance-variation equalizing distribution of at least one printed circuit board element operably coupled with the substantially mismatched impedance printed circuit board components;

the at least one printed circuit board element which renders impedance variations above and below a defined baseline impedance practicably equivalent; and

the one or more printed circuit boards operably connecting at least one processor and at least one memory.

13. The computer system of claim 12, wherein the at least one printed circuit board element which renders impedance variations above and below the defined baseline impedance practicably equivalent further includes:

the printed circuit board element having an associated inductive effect.

14. The computer system of claim 12, wherein the at least one printed circuit board element which renders impedance variations above and below the defined baseline impedance practicably equivalent further includes:

the printed circuit board element having an associated capacitive effect.

15. The computer system of claim 12, wherein the at least one printed circuit board element which renders impedance variations above and below the defined baseline impedance practicably equivalent further includes:

a first printed circuit board element having the associated inductive effect operably connected with a second printed circuit board element having the associated capacitive effect.

16. A computer system comprising:

one or more printed circuit boards having at least one circuit wherein reside substantially mismatched impedance printed circuit board components;

an impedance-variation equalizing distribution of at least one printed circuit board element operably coupled with the substantially mismatched impedance printed circuit board components;

the at least one printed circuit board element which renders impedance variations above and below a defined baseline impedance practicably equivalent; and

the one or more printed circuit boards operably connecting at least one processor and at least one memory;

wherein the substantially mismatched impedance printed circuit board components including at least one Connector Specification component operably connected with at least one non-Connector Specification component.

17. The computer system of claim 16, wherein the at least one Connector Specification component operably connected with at least one non-Connector Specification component further includes:

the at least one Connector Specification component operably connected with at least one PCI specification socket.

18. The computer system of claim 17, wherein the at least one Connector Specification component operably connected with the at least one PCI specification socket further includes:

a first PCI specification socket connector wiper and a second PCI specification socket connector wiper operably coupled by a shorting strap.

19. The computer system of claim 18, wherein the first PCI specification socket connector wiper and the second PCI specification socket connector wiper operably coupled by the shorting strap further includes:

a first and a second via on a first printed circuit board operably coupled by the shorting strap.

20. The computer system of claim 16, wherein the at least one Connector Specification component operably connected with the at least one non-Connector Specification component further includes:

the at least one Connector Specification component operably coupled with at least one non-Connector Specification fingerpad.

21. The computer system of claim 20, wherein the at least one Connector Specification component operably coupled with the at least one non-Connector Specification fingerpad further includes:

the at least one Connector Specification component operably coupled with a one-piece fingerpad.

22. The computer system of claim 16, wherein the at least one Connector Specification component operably connected with the at least one non-Connector Specification component further includes:

the at least one Connector Specification component operably coupled with at least one via.

23. The computer system of claim 16, wherein the at least one Connector Specification component operably connected with the at least one non-Connector Specification component further includes:

the at least one Connector Specification component operably coupled with at least one compensation pad.