Activ shunt-peaked logic gates

• US 6,788,103 B1
• Filed: 08/06/2002
• Issued: 09/07/2004
• Est. Priority Date: 08/06/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Aeluros, Inc. (Broadcom, Inc.)
• Inventors: Loinaz, Marc J., Feldman, Arnold R.
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/213,484
• Time in Patent Office: 763 Days
• Field of Search: 326/26, 326/27, 326/31, 326/34, 326/83, 326/86, 326/112, 326/1, 326/119, 326/121, 326/115, 326/126, 326/127
• US Class Current: 326/34
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic.

Claims

1. A circuit comprising:

at least one logic gate comprising at least two differential inputs lines and at least two differential output lines;

at least two resistive elements coupled to a biasing voltage; and

at least two transistors, each one of said transistors is coupled in series to one of said resistive elements so as to provide an inductance between said differential output lines and said resistive elements.

2. The circuit as set forth in claim 1, wherein said logic gate comprises metal oxide semiconductor (MOS) transistors configured using current-mode logic.

3. The circuit as set forth in claim 1, wherein said transistors comprise MOS transistors, wherein a gate of each of said MOS transistors is coupled to one of said resistive elements, a drain of each of said MOS transistors is coupled to a power supply voltage, a source of said MOS transistors is coupled to said differential output lines.

4. The circuit as set forth in claim 1, wherein said logic gate comprises bipolar transistors configured using emitter-coupled logic.

5. The circuit as set forth in claim 4, wherein said transistors comprise bipolar transistors, wherein a base of each of said bipolar transistors is coupled to one of said resistive elements, a collector of each of said bipolar transistors is coupled to a power supply voltage, an emitter of said bipolar transistors is coupled to said differential output lines.

6. The circuit as set forth in claim 1, wherein said logic gate comprises a latch.

7. The circuit as set forth in claim 1, wherein said logic gate comprises a multiplexor.

8. A method for high-speed switching of a logic gate, said method comprising the steps of:

providing at least one logic gate comprising at least two inputs lines and at least two differential output lines;

coupling a first resistive element to a biasing voltage;

coupling said first resistive element in series to a first transistor such that said first transistor provides an inductance between a first differential output line of said logic gate and said first resistive element;

coupling a second resistive element to a biasing voltage; and

coupling said second resistive element in series to a second transistor such that said second transistor provides an inductance between a second differential output line of said logic gate and said second resistive element.

9. The method as set forth in claim 8, wherein said logic gate comprises metal oxide semiconductor (MOS) transistors configured using current-mode logic.

10. The method as set forth in claim 9, wherein said transistors comprise MOS transistors, wherein a gate of each of said MOS transistors is coupled to one of said resistive elements, a drain of each of said MOS transistors is coupled to a power supply voltage, a source of said MOS transistors is coupled to said differential output lines.

11. The method as set forth in claim 8, wherein said logic gate comprises bipolar transistors configured using emitter-coupled logic.

12. The method as set forth in claim 11, wherein said transistors comprise bipolar transistors, wherein a base of each of said bipolar transistors is coupled to one of said resistive elements, a collector of each of said bipolar transistors is coupled to a power supply voltage, an emitter of said bipolar transistors is coupled to said differential output lines.

13. The method as set forth in claim 8, wherein said logic gate comprises a latch.

14. The circuit as set forth in claim 8, wherein said logic gate comprises a multiplexor.

15. A circuit comprising:

at least one logic gate comprising an input line and an output line;

a resistive element coupled to a biasing voltage; and

a transistor, coupled in series to said resistive element, so as to provide an inductance between said output line and said resistive element.

16. The circuit as set forth in claim 15, wherein said logic gate comprises metal oxide semiconductor (MOS) transistors configured using current-mode logic.

17. The circuit as set forth in claim 16, wherein said transistor comprises a MOS transistor, wherein a gate of said MOS transistor is coupled to said resistive element, a drain of said MOS transistor is coupled to a power supply voltage, and a source of said MOS transistor is coupled to a differential output line.

18. The circuit as set forth in claim 15, wherein said logic gate comprises bipolar transistors configured using emitter-coupled logic.

19. The circuit as set forth in claim 18, wherein said transistor comprises a bipolar transistor, wherein a base of said bipolar transistors is coupled to said resistive element, a collector of said bipolar transistor is coupled to a power supply voltage, and an emitter of said bipolar transistor is coupled to said differential output line.

20. The circuit as set forth in claim 15, wherein said logic gate comprises a latch.

21. The circuit as set forth in claim 15, wherein said logic gate comprises a multiplexor.

22. A circuit comprising:

at least one multi-stage logic gate comprising at least two differential inputs lines and at least two differential output lines, said multi-stage logic gate comprising more than a single logic stage;

at least two resistive elements; and

at least two inductive elements, each one of said inductive elements is coupled in series to one of said resistive elements and is coupled to one of said outputs such that said inductive elements couple said differential output lines to a power supply input.

23. The circuit as set forth in claim 22, wherein said multi-stage logic gate comprises a latch.

24. The circuit as set forth in claim 22, wherein said multi-stage logic gate comprises a multiplexor.

25. A circuit comprising:

at least one multi-stage logic gate comprising an input line and an output line, said multi-stage logic gate comprising more than a single logic stage;

a resistive element; and

at least one inductive element, coupled to said resistive element and coupled to said output such that said inductive element couples said output line to a power supply input.

26. The circuit as set forth in claim 25, wherein said multi-stage logic gate comprises a latch.

27. The circuit as set forth in claim 25, wherein said multi-stage logic gate comprises a multiplexor.

28. A circuit comprising:

at least one logic gate comprising at least two differential inputs lines and at least two differential output lines;

at least two resistive elements, each of said resistive element is coupled to a biasing voltage; and

at least two MOS transistors, each one of said transistors is coupled to one of said resistive elements and is coupled to one of said differential output lines such that said transistors couple said differential output lines to a power supply input, wherein a gate of each of said MOS transistors is coupled to one of said resistive elements, a drain of each of said MOS transistors is coupled to a power supply voltage, and a source of each of said MOS transistors is coupled to said differential output lines.

29. A circuit comprising:

at least one logic gate comprising at least two differential inputs lines and at least two differential output lines;

at least two resistive elements, each of said resistive element is coupled to a biasing voltage; and

at least two bipolar transistors, each one of said transistors is coupled to one of said resistive elements and is coupled to one of said differential output lines such that said transistors couples said differential output lines to a power supply input, wherein a base of each of said bipolar transistors is coupled to one of said resistive elements, a collector of each of said bipolar transistors is coupled to a power supply voltage, and an emitter of each of said bipolar transistors is coupled to said differential output lines.