Efficient charge pump capable of high voltage operation

• US 6,788,130 B2
• Filed: 09/25/2002
• Issued: 09/07/2004
• Est. Priority Date: 09/25/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Baldwin, David, Carpenter, John H. Jr., Pauletti, Timothy P.
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US10/254,336
• Publication Number:
  US 20040056707A1
• Time in Patent Office: 713 Days
• Field of Search: 327/536, 327/537, 363/59
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage higher than the high voltage reference. The integrated circuit includes a high voltage ground reference circuit, operable to provide a high voltage ground reference node. Also included is an oscillator, operable to provide a clock signal, the oscillator being connected to the high voltage reference and to the high voltage ground reference node. An isolated charge pump circuit is provided, operable to generate the output voltage and isolated in the integrated circuit from other circuitry.

Claims

1. A high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage higher than the high voltage reference, comprising:

a bias current generator stage coupled to receive the low voltage reference to generate a bias current;

a high voltage ground reference circuit coupled to receive the bias current, the low voltage reference, the high voltage reference and ground, the high voltage ground reference circuit operable to provide a high voltage ground reference node;

an oscillator, operable to provide a clock signal, the oscillator being connected to the high voltage reference and to the high voltage ground reference node; and

an isolated charge pump circuit coupled to receive the clock signal, the high voltage reference and an inverted clock signal, the isolated charge pump circuit operable to generate the output voltage.

2. A high voltage integrated circuit as in claim 1, wherein the high voltage ground reference circuit comprises an operational amplifier.

3. A high voltage integrated circuit as in claim 1, wherein the oscillator comprises a ring oscillator including PMOS FET devices in an n-type tank residing in a p-epi layer.

4. A high voltage integrated circuit as in claim 1, wherein the bias current generator stage, comprises:

a first transistor, having a gate node, a source node and a drain node, the source node coupled to receive the low voltage reference;

a second transistor, having a gate node, a source node and a drain node, the gate node coupled to the gate node of the first transistor, the drain node coupled to the drain node of the first transistor, the source node coupled to the ground;

a third transistor, having a gate node, a source node and a drain node, the gate node coupled to the gate node of the first transistor, the source node coupled to the ground; and

a current mirror coupled between the drain node of the third transistor and the low voltage reference.

5. A high voltage integrated circuit as in claim 1, wherein the oscillator, comprises:

a ring oscillator coupled to receive the high ground voltage reference, ground, and the high voltage reference to provide a clock signal;

a capacitor coupled across the high voltage reference and the high ground voltage reference; and

an inverter coupled to the ring oscillator to provide an inverted clock signal, wherein the inverter having a first and second control input coupled to receive the high ground voltage reference and the high voltage reference.

6. A high voltage integrated circuit as in claim 1, wherein the isolated charge pump circuit, comprises:

at least one stage that comprises,

a first transistor, having a control node, a drain node and a source node, the source node coupled to receive the high voltage reference,

a second transistor, having a control node, a drain node and a source node, the control node of the first transistor coupled to the control node of the second transistor, the drain node of the first transistor coupled to the drain node of the second transistor,

a third transistor, having a control node, a drain node and a source node, the source node coupled to receive the high voltage reference, the drain node coupled to the control node of the first transistor, the drain node of the first transistor coupled to the control node of the third transistor, and

a fourth transistor, having a control node, a drain node and a source node, the control node of the third transistor coupled to the control node of the fourth transistor, the drain node of the third transistor coupled to the drain node of the fourth transistor,

a first capacitor coupled between the drain node of the first transistor and the inverted clock signal node,

a second capacitor coupled between the drain node of the third transistor and the clock signal node

wherein each of the at least one stages couples to one preceding stage.