Power amplifier circuitry and method

• US 6,788,141 B2
• Filed: 03/18/2003
• Issued: 09/07/2004
• Est. Priority Date: 09/12/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Paul, Susanne A., Dupuis, Timothy J.
• Primary Examiner(s): Shingleton, Michael B.
• Application Number:
  US10/390,935
• Publication Number:
  US 20030179045A1
• Time in Patent Office: 539 Days
• Field of Search: 330/252, 330/253, 330/277
• US Class Current: 330/252
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/391 the output circuit of an amplifying stage comprising an LC-network
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03F 3/2176 : Class E amplifiers
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/30 : Single-ended push-pull [SEPP] amplifiers single-ended sense amplifiers G11C7/067; Phase-splitters therefor
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/04163 : in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 : using complementary field-effect transistors
• CPC Class Codes: Y10S 257/904 : with passive components,, e.g. polysilicon resistors

Abstract

A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Claims

1. A power amplifier comprising:

a first switching device connected between a first supply voltage and a first output node;

a second switching device connected between a second supply voltage and a second output node;

an inductance connected between the first and second output nodes; and

a first capacitor coupled to the first output node, wherein the first capacitor is provided by the input capacitance of a thud switching device.

2. The power amplifier of claim 1, wherein a load is coupled to the second output node.

3. The power amplifier of claim 1, further comprising a first capacitor coupled to the first output node.

4. The power amplifier of claim 1, further comprising a first capacitor coupled to the first output node, and a second capacitor coupled to the second output node.

5. The power amplifier of claim 4, wherein the first capacitor is provided by the input capacitance of a third switching device, and wherein the second capacitor is provided by the input capacitance of a fourth switching device.

6. The power amplifier of claim 1, further comprising a first capacitor coupled between the first and second output nodes.

7. The power amplifier of claim 1, wherein the first and second switching devices are driven by signals that repeatedly turn the devices on and off.

8. The power amplifier of claim 7, wherein the first and second switching devices are both cycled on during the same time period, and wherein the first and second switching devices are both cycled off during the same time period.

9. The power amplifier of claim 1, wherein the first and second switching devices are comprised of transistors.

10. The power amplifier of claim 1, wherein the first switching device is comprised of a PMOS transistor, and wherein the second switching device is comprised of an NMOS transistor.

11. The power amplifier of claim 1, further comprising a load coupled across the first and second output nodes.

12. The power amplifier of claim 1, further comprising a transformation network coupled to the first and second output nodes.

13. The power amplifier of claim 12, wherein the transformation network further comprises:

a capacitor coupled to the first output node and a third node;

an inductor coupled to the second output node and the third node; and

a load coupled to the third node.

14. The power amplifier of claim 1, further comprising a preamplifier connected to the power amplifier, the preamplifier further comprising:

a third switching device connected between said first supply voltage and a third node and coupled to the input of the first switching device;

a fourth switching device connected between said second supply voltage and a fourth node and coupled to the input of the second switching device; and

a second inductor coupled between the third and fourth nodes.

15. A The power amplifier or claim 1, further comprising one or more inductors coupled between the first output node and a third supply voltage.

16. The power amplifier of claim 1, further comprising one or more inductors coupled between the first output node and a third supply voltage, and one or more inductors coupled between the second output node and a fourth supply voltage.

17. The power amplifier of claim 1, wherein the inductance is provided by an inductor.

18. The power amplifier of claim 17, wherein the inductor has a first terminal and a second terminal, wherein the first terminal is connected to the first output node and the second terminal is connected to the second output node.

19. The power amplifier of claim 17, wherein the inductor has a first terminal and a second terminal, wherein the first terminal is connected to a terminal of the first switching device and the second terminal is connected to a terminal of the second switching device.

20. A method of reducing the peak output voltage of an amplifier comprising the steps of:

providing an inductor having first and second terminals;

providing a first switching device connected to the first terminal of the inductor and to a first supply voltage;

providing a second switching device connected to the second terminal of the inductor and a second supply voltage;

applying a voltage between the first and second terminals of the inductor during a first portion of a clock cycle by turning on the first and second switching devices;

turning off the first and second switching devices during a second portion of the clock cycle; and

driving the first and second switching devices such that the switching devices are turned on and off simultaneously.

21. The method of claim 20, further comprising the steps of providing a first capacitance connected to the first terminal, providing a second capacitance connected to the second terminal, wherein current from the inductor charges or discharges the first and second capacitances during the second portion of the clock cycle.

22. The method of claim 20, further comprising the step of connecting a load to the first node.

23. The method of claim 22, wherein the load includes a reactive network.

24. The method of claim 20, further comprising the step of driving the first and second switching devices by repeatedly turning both devices on and then turning both devices off.

25. The method of claim 20, wherein the switching devices are comprised of transistors.

26. The method of claim 20, further comprising the step of differentially connecting a loud to the first and second nodes.

27. The method of claim 20, wherein a load is connected across the first and second nodes.

28. The method of claim 20, further comprising the steps of:

providing a third switching device connected between the gate of the first switching device and a third supply voltage;

providing a fourth switching device connected between the gate of the second switching device and a fourth supply voltage; and

providing a second inductor connected between the gates of the first and second switching devices.

29. A power amplifier comprising:

a first switching device connected between a first supply voltage and a first output node;

a second switching device connected between a second supply voltage and a second output node;

an inductance connected between the first and second output nodes; and

a transformation network coupled to the first and second output nodes, wherein the transformation network further comprises a capacitor coupled to the first output node and a third node, an inductor coupled to the second Output node and the third node, and a load coupled to the third node.

30. The power amplifier of claim 29, further comprising a first capacitor coupled to the first output node.

31. The power amplifier of claim 30, wherein the first capacitor is provided by the input capacitance of a third switching device.

32. The power amplifier of claim 29, wherein the first and second switching devices are driven by signals that repeatedly turn the devices on and off.

33. The power amplifier of claim 32, wherein the first and second switching devices are both cycled on during the same time period, and wherein the first and second switching devices are both cycled off during the same time period.

34. The power amplifier of claim 29, further comprising a load coupled across the first and second output nodes.

35. A power amplifier comprising:

a first switching device connected between a first supply voltage and a first output node;

a second switching device connected between a second supply voltage and a second output node;

an inductance connected between the first and second output nodes; and

a preamplifier connected to the power amplifier, the preamplifier further comprising;

a third switching device connected between said first supply voltage and a third node and coupled to the input of the first switching device;

a fourth switching device connected between said second supply voltage and a fourth node and coupled to the input of the second switching device; and

a second inductor coupled between the third and fourth nodes.

36. The power amplifier of claim 35, wherein the first and second switching devices are driven by signals that repeatedly turn the devices on and off.

37. The power amplifier of claim 36, wherein the first and second switching devices are both cycled on during the same time period, and wherein the first and second switching devices are both cycled off during the same time period.

38. The power amplifier of claim 35, further comprising a load coupled across the first and second output nodes.

39. The power amplifier of claim 35, further comprising a transformation network coupled to the first and second output nodes.

40. A power amplifier comprising:

a first switching device connected between a first supply voltage and a first output node;

a second switching device connected between a second supply voltage and a second output node;

an inductance connected between the first and second output nodes; and

one or more inductors coupled between the first output node and a third supply voltage.

41. The power amplifier of claim 40, further comprising a first capacitor coupled to the first output node.

42. The power amplifier of claim 41, wherein the first capacitor is provided by the input capacitance of a third switching device.

43. The power amplifier of claim 40, wherein the first and second switching devices are driven by signals that repeatedly turn the devices on and off.

44. The power amplifier of claim 43, wherein the first and second switching devices are both cycled on during the same time period, and wherein the first and second switching devices are both cycled off during the same time period.

45. The power amplifier of claim 40, further comprising a load coupled across the first and second output nodes.

46. A method of reducing the peak output voltage of an amplifier comprising the steps of:

providing an inductor having first and second terminals;

providing a first switching device connected to the first terminal of the inductor and to a first supply voltage;

providing a second switching device connected to the second terminal of the inductor and a second supply voltage;

applying a voltage between the first and second terminal of the inductor during a first portion of a clock cycle by turning on the first and second switching devices;

turning off the first and second switching devices during a second portion of the clock cycle; and

driving the first and second switching devices by repeatedly turning both devices on and then turning both devices off.

47. The method of claim 46, further comprising the steps of providing a first capacitance connected to the first terminal, providing a second capacitance connected to the second terminal, wherein current from the inductor charges or discharges the first and second capacitances during the second portion of the clock cycle.

48. The method of claim 46, further comprising the step of connecting a load to the first node.

49. The method of claim 48, wherein the load includes a reactive network.

50. The method of claim 46, further comprising the step of differentially connecting a load to the first and second nodes.

51. A method of reducing the peak output voltage of an amplifier comprising the steps of:

providing an inductor having first and second terminals;

providing a first switching device connected to the first terminal of the inductor and to a first supply voltage;

providing a second switching device connected to the second terminal of the inductor and a second supply voltage;

applying a voltage between the first and second terminals of the inductor during a first portion of a clock cycle by turning on the first and second switching devices;

turning off the first and second switching devices during a second portion of the clock cycle;

providing a third switching device connected between the gate of the first switching device and a third supply voltage;

providing a fourth switching device connected between the gate of the second switching device and a fourth supply voltage; and

providing a second inductor connected between the gates of the first and second switching devices.

52. The method of claim 51, further comprising the step of driving the first and second switching devices such that the switching devices are turned on and off simultaneously.

53. The method of claim 51, further comprising the step of driving the first and second switching devices by repeatedly turning both devices on and then turning both devices off.