Digital imaging control with selective intensity resolution enhancement

• US 6,788,340 B1
• Filed: 12/30/1999
• Issued: 09/07/2004
• Est. Priority Date: 03/15/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Clynes, Steven Derek, Liu, Anli, Dierschke, Eugene G., Chen, Zhiliang Julian
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Rosendale, Matthew L
• Application Number:
  US09/475,901
• Time in Patent Office: 1,713 Days
• Field of Search: 348/229.1, 348/241, 348/243, 396/161, 396/213, 396/219, 330/96
• US Class Current: 348/229.1
• CPC Class Codes: H04N 23/76 by influencing the image signals
• CPC Class Codes: H04N 25/68 applied to defects
• CPC Class Codes: H04N 25/69 SSIS comprising testing or correcting structures for circuits other than pixel cells
• CPC Class Codes: H04N 5/20 Circuitry for controlling amplitude response

Abstract

Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Claims

1. A method of automatic gain control in an image processor having a programmable amplifier, the programmable amplifier having a reference voltage input and a signal input and a programmable gain value and having a differential output coupled to an analog to digital converter (ADC), the analog to digital converter outputting a digital code corresponding to the output of the programmable amplifier, the method comprising:

reading a frame of luminance data,

determining an average luminance value of the frame and the digital code output by the ADC corresponding to average luminance value;

calculating a reference voltage that will cause the digital code output by the ADC to be at a target value when the input to the programmable amplifier is set to the average luminance value;

calculating a gain that will cause the digital code output by the ADC to be at the target value when the input to the programmable amplifier is set to the average luminance value;

setting the reference voltage and the gain to the calculated values and reading the next frame;

wherein the gain is calculated from the difference in (1) the digital code output by the ADC when the signal input to the programmable amplifier is set to the average luminance value, and (2) a pre-determined digital code output by the ADC.

2. The method of claim 1 further comprising:

reading an optically black portion of the frame in which the luminance value is at a known luminance reference value; and

calculating a reference voltage that will cause the output of the ADC to be at a desired minimum value when the input signal to the programmable amplifier is set to the known reference value.

3. The method of claim 2 wherein the steps occur automatically at the start of each frame.

4. The method of claim 1 wherein the steps of determining an average luminance value, calculating a reference voltage, calculating a gain, and setting the reference voltage and the gain to the calculated values occur automatically after each frame is read.

5. The method of claim 1 wherein the pre-determined output of the ADC is the mid-point of a range of ADC output values.

6. The method of claim 1 wherein the pre-determined output of the ADC is 75% of a maximum ADC output value.

7. An image processor comprising:

a differential amplifier receiving as input a luminance signal and a reference voltage signal and outputting an amplified differential signal;

a differential analog to digital converter (ADC) receiving as input said amplified differential signal and outputting a digital signal corresponding to said amplified differential signal;

a programmable voltage source outputting said reference voltage signal;

a digital averager receiving said digital signal and outputting an average luminance value;

a digital signal controller receiving said average luminance value and outputting a gain control signal to said differential amplifier and a reference voltage control signal to said programmable voltage source, the gain control signal and the reference voltage control signal being determined from the difference in (1) the digital signal of the analog to digital converter when the luminance input is at the average brightness value and (2) a desired digital signal.

8. The image processor of claim 7 wherein the reference voltage control signal is calculated from the output of the differential analog to digital converter by the equation delta(D_inm)≈

−

delta(D_outn)/2*g, wherein delta(D_inm) is the change in the input to a digital to analog converter controlling the programmable voltage source, delta(D_outn) is the change in the output of the analog to digital converter, and g is the gain of the differential amplifier.

9. The image processor of claim 7 wherein the amplified differential signal of the programmable amplifier is connected directly to the differential analog to digital converter.

10. The image processor of claim 7 wherein the digital signal output by the differential analog to digital converter has a maximum and a minimum value and the desired digital signal is mid-point between the maximum and minimum values.

11. The image processor of claim 7 wherein the digital signal output by the differential analog to digital converter has a maximum and a minimum value and the desired digital signal is about 75% of the maximum value.

12. The image processor of claim 7 wherein the image processor is realized in combinational logic.

13. The image processor of claim 7 wherein the gain is adjusted in multiples of two.

14. The image processor of claim 7 further comprising an integration interval calculation circuit wherein an integration interval is calculated from the difference in (1) the digital signal of the analog to digital converter when the luminance input is at the average luminance value and (2) the desired digital signal.

15. The image processor of claim 7 wherein the digital signal controller further outputs a second reference voltage control signal to said programmable voltage source, the second reference voltage control signal being determined so as to drive the output of the analog to digital converter to a desired minimum value when the luminance signal input to the differential amplifier is at optical black.

16. The image processor of claim 12 wherein the combinational logic operates in real time.

17. An automatic gain control circuit comprising:

an amplifier receiving as input a frame of a luminance signal and a reference voltage signal, and outputting a differential signal corresponding to the difference between the luminance signal and the reference voltage signal, the amplifier amplifying the difference under control of a gain control signal;

a differential analog to digital converter (ADC) receiving the signal output by the amplifier and outputting a digital signal corresponding to differential output of the amplifier;

means for calculating an average luminance value for the frame;

means for comparing the digital signal output by the ADC when the luminance signal input to the amplifier is at the average luminance value to a desired digital output and generating a difference signal;

means for adjusting the reference voltage signal in response to the difference signal; and

means for adjusting the gain control signal in response to the difference signal;

further including means for manually and independently adjusting the reference voltage signal, the gain, and the integration interval.