Thin film transistor substrate for a liquid crystal display and a method for repairing the substrate

• US 6,788,356 B2
• Filed: 05/23/2001
• Issued: 09/07/2004
• Est. Priority Date: 05/23/2000
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Jang-Kun
• Primary Examiner(s): Kim, Robert H.
• Assistant Examiner(s): QI, ZHI QIANG
• Application Number:
  US09/862,588
• Publication Number:
  US 20010046003A1
• Time in Patent Office: 1,203 Days
• Field of Search: 349/43, 349/158, 349/110, 349/130, 349/129, 349/141, 349/54
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136263 Line defects

Abstract

Disclosed is a thin film transistor substrate for a liquid crystal display and a method for repairing the substrate. The substrate comprises an insulating substrate; a black matrix formed on the insulating substrate having apertures in areas of pixels, shaped as a net; an insulating layer covering the black matrix; gate wiring formed on the insulating layer, the gate wiring including gate lines extended in a first direction across the substrate and gate electrodes connected to the gate lines; a gate insulating layer formed over the gate wiring; a semiconductor layer formed over the gate insulating layer; an ohmic contact layer formed over the semiconductor layer; data wiring including source electrodes and drain electrodes formed separated from each other over the ohmic contact layer, and data lines connected to the source electrodes and crossing the gate lines to define pixels; a protection layer formed over the data wiring; and pixel electrodes electrically connected to the drain electrodes. The method comprises the step of shorting the disconnected gate line and the first portion of the black matrix or the disconnected data line and the second portion of the black matrix.

Claims

1. A thin film transistor substrate for a liquid crystal display, comprising:

an insulating substrate;

a black matrix formed on said insulating substrate having apertures in areas of pixels and shaped as a net;

an insulating layer covering said black matrix;

a gate wiring formed on said insulating layer, said gate wiring including gate lines extended in a first direction across said substrate and gate electrodes connected to the gate lines;

a gate insulating layer formed over said gate wiring;

a semiconductor layer formed over said gate insulating layer;

an ohmic contact layer formed over said semiconductor layer;

a data wiring including source electrodes and drain electrodes formed separated from each other over said ohmic contact layer, and data lines connected to the source electrodes and crossing the gate lines to define the pixels;

a protection layer formed over said data wiring; and

pixel electrodes electrically connected to the drain electrodes.

2. The substrate of claim 1, further comprising a buffer layer formed on the same layer as said gate wiring and said data wiring, the buffer layer being formed between portions of the black matrix.

3. The substrate of claim 2, wherein the black matrix includes first portions overlapping the gate lines, and second portions separated from the first portions and overlapping the data lines.

4. The substrate of claim 3, wherein a portion of the black matrix overlapping the gate wiring or the data wiring is removed.

5. The substrate of claim 1, wherein the black matrix is formed overlapping adjacent pixel electrodes.

6. The substrate of claim 5, wherein a overlapping width of the pixel electrodes and the black matrix is in the range of 0.5-2 μ

m.

7. The substrate of claim 1, wherein the pixel electrodes and the data lines are spaced apart by a distance in the range of 2-6 μ

m.

8. The substrate of claim 1, wherein the insulating layer contains silicon oxide.

9. The substrate of claim 1, wherein the insulating layer is formed to a thickness of 0.5-3 μ

m.

10. The substrate of claim 1, wherein the substrate is used in a vertically-aligned liquid crystal display, in which liquid crystal molecules are aligned vertically to the substrate.

11. The substrate of claim 1, wherein liquid crystal molecules are aligned parallel to the substrate and the pixel electrodes are formed linearly, and which further comprises a linear common electrode opposing the pixel electrodes.

12. The substrate of claim 1, further comprising storage electrodes overlapping the pixel electrodes to form a storage capacitance.

13. A liquid crystal display, comprising:

an insulating first substrate;

a black matrix formed on said insulating first substrate having apertures in areas of pixels and shaped as a net;

an insulating layer covering said black matrix;

a gate wiring formed on said insulating layer, said gate wiring including gate lines extended in a first direction across the substrate and gate electrodes connected to the gate lines;

a gate insulating layer formed over said gate wiring;

a semiconductor layer formed over said gate insulating layer;

an ohmic contact layer formed over said semiconductor layer;

a data wiring including source electrodes and drain electrodes formed separated from each other over said ohmic contact layer, and data lines connected to the source electrodes and crossing the gate lines to define the pixels;

a protection layer formed over said data wiring;

a pixel wiring including pixel electrodes electrically connected to the drain electrodes through contact holes formed in said protection layer;

an insulating second substrate provided opposing said insulating first substrate; and

a common electrode formed on said insulating second substrate, said common electrode opposing the pixel electrodes to form an electric field for driving liquid crystal molecules.

14. The liquid crystal display of claim 13, further comprising a buffer layer formed on the same layer as said gate wiring and said data wiring, the buffer layer being formed between portions of said black matrix.

15. The liquid crystal display of claim 14, wherein said black matrix includes first portions overlapping the gate lines, and second portions separated from the first portions and overlapping the data lines.

16. The liquid crystal display of claim 13, wherein the liquid crystal molecules are aligned vertically to said insulating first substrate and said insulating second substrate.