Safety net paradigm for managing two computer execution modes

• US 6,789,181 B1
• Filed: 11/03/1999
• Issued: 09/07/2004
• Est. Priority Date: 01/28/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Yates, John S., Reese, David L., Van Dyke, Korbin S., Hohensee, Paul H.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/432,753
• Time in Patent Office: 1,770 Days
• Field of Search: 712/4, 703/22, 714/37
• US Class Current: 712/4
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

Claims

1. A method of executing a program in a computer, comprising the steps of:

translating a source program into an object program, the translated object program having a different execution behavior than the source program;

executing the translated object program, the execution being under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed; and

when the monitor detects the deviation, or when an interrupt occurs during execution of the object program, establishing a state of the program corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue, and continuing execution of the source program primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

2. A method of executing a program in a computer, comprising the steps of:

executing instructions in a first interpreter for executing instructions of an instruction set, the first interpreter being less than fully correct, the execution being under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the incorrect interpretation is irreversibly committed; and

when the monitor detects the deviation, continuing execution in a second, fully-correct interpreter, primarily in hardware, for executing instructions of the instruction set.

3. The method of claim 2, further comprising the step of:

the detecting of a deviation includes evaluating whether an individual memory reference of an instruction references a device having a valid memory address but that cannot be guaranteed to be well-behaved.

4. The method of claim 2:

wherein the first interpreter includes a binary translator from the instruction set to a second instruction set, the translation distinguishing individual memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s); and

wherein detecting the deviation includes identifying a load that was believed at translation time to be directed to well-behaved memory but that at execution is found to be directed to non-well-behaved memory.

5. The method of claim 2:

wherein the first interpreter includes a binary translator from the instruction set to a second instruction set, the translation altering an ordering of side-effects of the program;

further comprising the step of, when an interrupt occurs during execution of the program in the second instruction set, establishing a state of the program corresponding to the earlier point, being a state equivalent to a state that would have occurred during an execution of the program in the first instruction set;

reinitiating execution of the program in the first instruction set.

6. The method of claim 2, further comprising the steps of:

wherein the first interpreter includes a binary translator from the instruction set to a second instruction set, the translated program in the second instruction set having a different execution behavior that the program in the first instruction set;

further comprising the step of, when an interrupt occurs during execution of the program in the second instruction set, establishing a state of the program corresponding to a state that would have occurred during an execution of the program in the first instruction set, and from which execution can continue;

executing program in the first instruction set from the established state.

7. The method of claim 2, wherein the second interpreter interprets instructions in an instruction set not native to the computer.

8. The method of claim 2, wherein the first interpreter includes a software binary translator.

9. The method of claim 8, wherein the detected deviation from fully-correct interpretation includes detection of the invalidity of a program transformation introduced by the binary translator.

10. The method of claim 2, wherein the earlier point corresponds to an instruction boundary.

11. The method of claim 2, wherein continuing execution includes rolling back execution of the first interpreter by at least two full instructions.

12. The method of claim 2, wherein continuing execution includes rolling back execution of the first interpreter from a state in which a number of distinct suboperations of several instructions have been intermixed by the first interpreter.

13. The method of claim 2, wherein continuing execution includes rolling back execution to a checkpoint.

14. The method of claim 2, wherein continuing execution includes allowing execution to progress forward to a checkpoint in the first interpreter.

15. The method of claim 2, wherein the detected deviation from fully-correct interpretation includes detection of a synchronous execution exception.

16. A computer, comprising:

a first interpreter designed to execute a program coded in an instruction set, the first interpreter being less than fully correct;

a second, fully-correct interpreter, primarily in hardware, for executing instructions of the instruction set;

a monitor designed to detect any deviation from fully-correct interpretation by the first interpreter, before any side-effect of the incorrect interpretation is irreversibly committed, and when the monitor detects the deviation, to roll back execution to an instruction boundary of the instruction set, and to re-initiate execution in the second interpreter.

17. The computer of claim 16, further comprising:

instruction execution circuitry of the first interpreter designed to evaluate whether an individual memory-reference instruction, or an individual memory reference of an instruction, references a device with a valid memory address that cannot be guaranteed to be well-behaved.

18. The computer of claim 16, wherein the first interpreter further comprises:

a binary translator from the instruction set to a second instruction set, the translation distinguishing individual memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s); and

instruction execution circuitry designed to execute the translated program in the second instruction set, and to identify loads that were believed at translation time to be directed to well-behaved memory but that at execution are found to be directed to non-well-behaved memory, and to abort the identified memory load.

19. The computer of claim 16, wherein the first interpreter includes:

a binary translator programmed to translate at least segment of a program from a first representation in the instruction set to a second representation in a second instruction set architecture, a sequence of side-effects in the second representation differing from a sequence of side-effects in the translated segment of the first representation; and

instruction execution circuitry and/or software designed to identify cases during execution of the second representation in which the difference in sequence of side-effects may have a material effect on the execution of the program, to establish a programs state equivalent to a state that would have occurred in the execution of the first representation, and to resume execution of the program from the established state in an execution mode that reflects the side-effect sequence of the first representation.

20. The computer of claim 16, wherein the first interpreter includes a software binary translator.

21. The computer of claim 20, wherein the first interpreter includes a software emulator.

22. The computer of claim 20, wherein the software binary translator operates concurrently with execution of the program to translate a segment less than the whole of the program.

23. The computer of claim 16, wherein the first interpreter includes a software emulator.

24. The computer of claim 16, wherein the second interpreter interprets instructions of an instruction set not native to the computer.

25. The computer of claim 16, wherein the earlier point corresponds to an instruction boundary.

26. The computer of claim 16, wherein continuing execution includes rolling back execution to a checkpoint.

27. The computer of claim 16, wherein the detected deviation from fully-correct interpretation includes detection of the invalidity of a program transformation introduced by the binary translator.

28. The computer of claim 16, wherein the detected deviation from fully-correct interpretation includes detection of a synchronous execution exception.

29. A method, comprising the steps of:

translating a source program into an object program, the translated object program having a different execution behavior than the source program;

when an interrupt occurs during execution of the object program, establishing a state of the program corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue;

executing the source program from the established state in a mode that executes or interprets the source program without re-translation into the language of the object program.

30. The method of claim 29, further comprising the step of:

establishing the state when a memory reference of an instruction executed during execution of the object program references a device having a valid memory address but that cannot be guaranteed to be well-behaved.

31. The method of claim 29:

while translating the source program from a first instruction set to the object program in a second instruction set, distinguishing individual memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s);

while executing the object program, identifying a load that was believed at translation time to be directed to well-behaved memory but that at execution is found to be directed to non-well-behaved memory, and aborting the identified memory load;

based at least in part on the identifying, re-executing at least a portion of the source program.

32. The method of claim 29, further comprising the step of:

translating the source program from a first instruction set with a reference sequence of side-effects to the object program in a second instruction set with a second sequence of side effects.

33. The method of claim 29, wherein the source program is coded in an instruction set not native to the computer.

34. The method of claim 29, wherein the translator operates concurrently with execution of the program to translate a segment less than the whole of the source program.

35. The method of claim 29, wherein establishing the state includes rolling back execution of the object program by at least two full instructions.

36. The method of claim 29, wherein establishing the state includes rolling back execution of the object program from a state in which a number of distinct suboperations of several instructions have been intermixed by the first interpreter.

37. The method of claim 29, wherein the interrupt is raised when a deviation from fully-correct translation of the program is detected.

38. The method of claim 29, wherein the interrupt is a synchronous execution exception.

39. The method of claim 29, wherein establishing the state includes rolling back execution to a checkpoint.

40. A computer, comprising:

a binary translator programmed to translate a source program into an object program, the translated object program having a different execution behavior than the source program;

an interrupt handler programmed to respond to an interrupt occurring during execution of the object program by establishing a state of the program corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue, and to initiate execution of the source program from the established state in a mode that executes or interprets the source program without re-translation into the language of the object program.

41. The computer of claim 40, further comprising:

instruction execution circuitry designed to evaluate whether an individual memory-reference instruction, or an individual memory reference of an instruction, references a device with a valid memory address that cannot be guaranteed to be well-behaved.

42. The computer of claim 40:

wherein the binary translator is programmed to generate a sequence of side-effects in the object program differing from a sequence of side-effects in the translated segment of the source program;

and further comprising, instruction execution circuitry and/or software designed to identify cases during execution of the object program in which the difference in sequence of side-effects may have a material effect on the execution of the program, to establish a program state equivalent to a state that would have occurred in the execution of the source program, and to resume execution of the program from the established state in an execution mode that reflects the side-effect sequence of the source program.

43. The computer of claim 40:

and further comprising instruction execution circuitry designed to execute the instruction set of the source program, being an instruction set not native to the computers;

a monitor designed to detect a deviation from the behavior of the source program during execution of the object program, before any side-effect of the deviation is irreversibly committed, and when the monitor detects the deviation, to roll back execution by at least a full instruction to a safe point in the program, and re-initiating execution in.

44. The computer of claim 40, wherein the source program is coded in an instruction set not native to the computer.

45. The computer of claim 40, wherein the established state corresponds to an instruction boundary.

46. The computer of claim 40, wherein the translator operates concurrently with execution of the object program to translate a segment less than the whole of the source program.

47. The computer of claim 40, wherein the interrupt is raised on detection of the invalidity of a program transformation introduced by the translator.

48. The computer of claim 40, wherein the interrupt is a synchronous execution exception.