Semiconductor integrated circuit device

• US 6,789,209 B1
• Filed: 07/13/2000
• Issued: 09/07/2004
• Est. Priority Date: 10/08/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Yasuharu, Suzuki, Takaaki
• Primary Examiner(s): Butler, Dennis M.
• Application Number:
  US09/615,952
• Time in Patent Office: 1,517 Days
• Field of Search: 713/400, 713/401, 713/500, 713/503, 713/600
• US Class Current: 713/401
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

In a semiconductor integrated circuit device operating in synchronism with a clock supplied from the outside of the device, there is provided a circuit generating, from the clock, an output strobe signal for outputting data from the device and outputting the output strobe signal to the outside of the device.

Claims

1. A semiconductor integrated circuit device which operates in synchronism with an external clock, the device comprising:

a first circuit to generate, from said external clock, an output strobe signal for outputting data from the device, and to output the output strobe signal,

said external clock including complementary clock components,

wherein receipt of input data, a command and an address are responsive to a cross point where the complementary clock components of said external clock cross a reference voltage.

2. The semiconductor integrated circuit device as claimed in claim 1, wherein said first circuit comprises a buffer circuit which buffers the clock, and a buffered clock is the output strobe signal.

3. The semiconductor integrated circuit device as claimed in claim 1, wherein said first circuit comprises a delayed lock loop circuit which controls the clock and the output strobe signal so as to have a given phase difference therebetween.

4. The semiconductor integrated circuit device as claimed in claim 1, wherein the output strobe signal includes complementary components.

5. The semiconductor integrated circuit device as claimed in claim 1, wherein:

the output strobe signal includes complementary components; and

a cross point of the complementary components of the output strobe signal defines a settlement period for output data.

6. The semiconductor integrated circuit device as claimed in claim 1, further comprising:

a second circuit which buffers the external clock and outputs a buffered clock as a strobe signal for input data.

7. A semiconductor memory device comprising:

a memory part;

a clock receiving part to receive external complementary clocks; and

a first circuit to generate, from said external complementary clocks, complementary output strobe signals for outputting data stored in the memory part, and to output the complementary output strobe signals,

wherein receipt of input data, a command and an address are responsive to a cross point where said external complementary clocks cross a reference voltage.

8. The semiconductor memory device as claimed in claim 7, wherein said first circuit comprises a buffer circuit which buffers the complementary clocks and outputs buffered complementary clocks as the complementary output strobe signals.

9. The semiconductor memory device as claimed in claim 7, wherein said first circuit comprises a delayed lock loop circuit which controls the complementary clocks and the complementary output strobe signals so as to have a given phase difference therebetween.

10. A system comprising:

a controller to output complementary clocks; and

a memory device coupled to the controller,

said memory device comprising;

a memory part;

a clock receiving part to receive the complementary clocks; and

a first circuit to generate, from said complementary clocks, complementary output strobe signals for outputting data stored in the memory part, and to output the complementary output strobe signals to the controller,

wherein receipt of input data, a command and an address are responsive to a cross point where said complementary clocks cross a reference voltage.

11. The system as claimed in claim 10, wherein said first circuit comprises a buffer circuit which buffers the complementary clocks and outputs buffered complementary clocks as the complementary output strobe signals.

12. The system as claimed in claim 10, wherein said first circuit comprises a delayed lock loop circuit which controls the complementary clocks and the complementary output strobe signals so as to have a given phase difference therebetween.