Method and apparatus for vector processing
First Claim
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1. In an integrated circuit configured to receive a test pattern from a test pattern generator and to provide test data in response to the test pattern, a response analyzer comprising:
- a shift register configured to receive a plurality of inputs representing the test data and to provide a plurality of outputs fewer in number than the plurality of inputs; and
a multiple-input signature register configured to receive the plurality of outputs and to compress the plurality of outputs.
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Abstract
A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.
48 Citations
21 Claims
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1. In an integrated circuit configured to receive a test pattern from a test pattern generator and to provide test data in response to the test pattern, a response analyzer comprising:
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a shift register configured to receive a plurality of inputs representing the test data and to provide a plurality of outputs fewer in number than the plurality of inputs; and
a multiple-input signature register configured to receive the plurality of outputs and to compress the plurality of outputs. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for compression of a vector, comprising:
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providing a shift register;
providing a multiple-input signature register coupled to the shift register;
shifting out bits of the vector with the shift register to provide an output with a bit output width less than a bit length of the vector;
providing the shifted out bits to the multiple-input signature register; and
compressing the vector with the multiple-input signature register to produce an output. - View Dependent Claims (8, 9, 10)
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11. A method for compression of a set of vectors, comprising:
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providing a shift register;
providing a multiple-input signature register coupled to the shift register, the multiple-input signature register input width narrower than input width of the shift register;
shifting out bits for each vector of the set of vectors with the shift register;
providing the shifted out bits to the multiple-input signature register; and
compressing the set of vectors to produce an output vector having an output length corresponding to the input width of the multiple-input signature register. - View Dependent Claims (12)
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13. A response analyzer for built-in self-test circuitry, comprising:
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a first stage configured to receive an input test vector and to provide said input test vector a portion at a time, wherein said portion is narrower in bit width than said input test vector length; and
a second stage configured to receive each said portion and to compress said input test vector to provide an output. - View Dependent Claims (14, 15)
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16. A response analyzer for built-in self-test circuitry, comprising:
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a first shift register configured to receive each test data vector of a plurality of test data vectors and to output each said test data vector a portion at a time, wherein said portion has fewer bits in output width than each said test data vector length; and
a second shift register configured to receive each said portion and to compress each said test data vector, said second shift register configured with feedback. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification